misc.hh revision 7306:548a5ee3dc5f 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_ARM_INSTS_MISC_HH__
41#define __ARCH_ARM_INSTS_MISC_HH__
42
43#include "arch/arm/insts/pred_inst.hh"
44
45class MrsOp : public PredOp
46{
47  protected:
48    IntRegIndex dest;
49
50    MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
51            IntRegIndex _dest) :
52        PredOp(mnem, _machInst, __opClass), dest(_dest)
53    {}
54
55    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
56};
57
58class MsrBase : public PredOp
59{
60  protected:
61    uint8_t byteMask;
62
63    MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
64            uint8_t _byteMask) :
65        PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
66    {}
67
68    void printMsrBase(std::ostream &os) const;
69};
70
71class MsrImmOp : public MsrBase
72{
73  protected:
74    uint32_t imm;
75
76    MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
77             uint32_t _imm, uint8_t _byteMask) :
78        MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
79    {}
80
81    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
82};
83
84class MsrRegOp : public MsrBase
85{
86  protected:
87    IntRegIndex op1;
88
89    MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
90             IntRegIndex _op1, uint8_t _byteMask) :
91        MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
92    {}
93
94    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
97class ImmOp : public PredOp
98{
99  protected:
100    uint32_t imm;
101
102    ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
103             uint32_t _imm) :
104        PredOp(mnem, _machInst, __opClass), imm(_imm)
105    {}
106
107    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
108};
109
110class RegRegOp : public PredOp
111{
112  protected:
113    IntRegIndex dest;
114    IntRegIndex op1;
115
116    RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
117             IntRegIndex _dest, IntRegIndex _op1) :
118        PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
119    {}
120
121    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
122};
123
124class RegImmRegOp : public PredOp
125{
126  protected:
127    IntRegIndex dest;
128    uint32_t imm;
129    IntRegIndex op1;
130
131    RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
132                IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
133        PredOp(mnem, _machInst, __opClass),
134        dest(_dest), imm(_imm), op1(_op1)
135    {}
136
137    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
138};
139
140class RegRegRegImmOp : public PredOp
141{
142  protected:
143    IntRegIndex dest;
144    IntRegIndex op1;
145    IntRegIndex op2;
146    uint32_t imm;
147
148    RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
149                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
150                   uint32_t _imm) :
151        PredOp(mnem, _machInst, __opClass),
152        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
153    {}
154
155    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
156};
157
158class RegRegRegRegOp : public PredOp
159{
160  protected:
161    IntRegIndex dest;
162    IntRegIndex op1;
163    IntRegIndex op2;
164    IntRegIndex op3;
165
166    RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
167                   IntRegIndex _dest, IntRegIndex _op1,
168                   IntRegIndex _op2, IntRegIndex _op3) :
169        PredOp(mnem, _machInst, __opClass),
170        dest(_dest), op1(_op1), op2(_op2), op3(_op3)
171    {}
172
173    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
174};
175
176class RegRegRegOp : public PredOp
177{
178  protected:
179    IntRegIndex dest;
180    IntRegIndex op1;
181    IntRegIndex op2;
182
183    RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
184                IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
185        PredOp(mnem, _machInst, __opClass),
186        dest(_dest), op1(_op1), op2(_op2)
187    {}
188
189    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
190};
191
192class RegRegImmImmOp : public PredOp
193{
194  protected:
195    IntRegIndex dest;
196    IntRegIndex op1;
197    uint32_t imm1;
198    uint32_t imm2;
199
200    RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
201                   IntRegIndex _dest, IntRegIndex _op1,
202                   uint32_t _imm1, uint32_t _imm2) :
203        PredOp(mnem, _machInst, __opClass),
204        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
205    {}
206
207    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
208};
209
210class RegImmRegShiftOp : public PredOp
211{
212  protected:
213    IntRegIndex dest;
214    uint32_t imm;
215    IntRegIndex op1;
216    int32_t shiftAmt;
217    ArmShiftType shiftType;
218
219    RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
220                     IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
221                     int32_t _shiftAmt, ArmShiftType _shiftType) :
222        PredOp(mnem, _machInst, __opClass),
223        dest(_dest), imm(_imm), op1(_op1),
224        shiftAmt(_shiftAmt), shiftType(_shiftType)
225    {}
226
227    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
228};
229
230#endif
231