misc.hh revision 10037
1/* 2 * Copyright (c) 2010, 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_ARM_INSTS_MISC_HH__ 41#define __ARCH_ARM_INSTS_MISC_HH__ 42 43#include "arch/arm/insts/pred_inst.hh" 44 45class MrsOp : public PredOp 46{ 47 protected: 48 IntRegIndex dest; 49 50 MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 51 IntRegIndex _dest) : 52 PredOp(mnem, _machInst, __opClass), dest(_dest) 53 {} 54 55 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 56}; 57 58class MsrBase : public PredOp 59{ 60 protected: 61 uint8_t byteMask; 62 63 MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 64 uint8_t _byteMask) : 65 PredOp(mnem, _machInst, __opClass), byteMask(_byteMask) 66 {} 67 68 void printMsrBase(std::ostream &os) const; 69}; 70 71class MsrImmOp : public MsrBase 72{ 73 protected: 74 uint32_t imm; 75 76 MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 77 uint32_t _imm, uint8_t _byteMask) : 78 MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm) 79 {} 80 81 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 82}; 83 84class MsrRegOp : public MsrBase 85{ 86 protected: 87 IntRegIndex op1; 88 89 MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 90 IntRegIndex _op1, uint8_t _byteMask) : 91 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1) 92 {} 93 94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 95}; 96 97class MrrcOp : public PredOp 98{ 99 protected: 100 IntRegIndex op1; 101 IntRegIndex dest; 102 IntRegIndex dest2; 103 uint32_t imm; 104 105 MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 106 IntRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, 107 uint32_t _imm) : 108 PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest), 109 dest2(_dest2), imm(_imm) 110 {} 111 112 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 113}; 114 115class McrrOp : public PredOp 116{ 117 protected: 118 IntRegIndex op1; 119 IntRegIndex op2; 120 IntRegIndex dest; 121 uint32_t imm; 122 123 McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 124 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _dest, 125 uint32_t _imm) : 126 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2), 127 dest(_dest), imm(_imm) 128 {} 129 130 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 131}; 132 133class ImmOp : public PredOp 134{ 135 protected: 136 uint64_t imm; 137 138 ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 139 uint64_t _imm) : 140 PredOp(mnem, _machInst, __opClass), imm(_imm) 141 {} 142 143 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 144}; 145 146class RegImmOp : public PredOp 147{ 148 protected: 149 IntRegIndex dest; 150 uint64_t imm; 151 152 RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 153 IntRegIndex _dest, uint64_t _imm) : 154 PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm) 155 {} 156 157 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 158}; 159 160class RegRegOp : public PredOp 161{ 162 protected: 163 IntRegIndex dest; 164 IntRegIndex op1; 165 166 RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 167 IntRegIndex _dest, IntRegIndex _op1) : 168 PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 169 {} 170 171 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 172}; 173 174class RegImmRegOp : public PredOp 175{ 176 protected: 177 IntRegIndex dest; 178 uint64_t imm; 179 IntRegIndex op1; 180 181 RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 182 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) : 183 PredOp(mnem, _machInst, __opClass), 184 dest(_dest), imm(_imm), op1(_op1) 185 {} 186 187 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 188}; 189 190class RegRegRegImmOp : public PredOp 191{ 192 protected: 193 IntRegIndex dest; 194 IntRegIndex op1; 195 IntRegIndex op2; 196 uint64_t imm; 197 198 RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 199 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 200 uint64_t _imm) : 201 PredOp(mnem, _machInst, __opClass), 202 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 203 {} 204 205 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 206}; 207 208class RegRegRegRegOp : public PredOp 209{ 210 protected: 211 IntRegIndex dest; 212 IntRegIndex op1; 213 IntRegIndex op2; 214 IntRegIndex op3; 215 216 RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 217 IntRegIndex _dest, IntRegIndex _op1, 218 IntRegIndex _op2, IntRegIndex _op3) : 219 PredOp(mnem, _machInst, __opClass), 220 dest(_dest), op1(_op1), op2(_op2), op3(_op3) 221 {} 222 223 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 224}; 225 226class RegRegRegOp : public PredOp 227{ 228 protected: 229 IntRegIndex dest; 230 IntRegIndex op1; 231 IntRegIndex op2; 232 233 RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 234 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 235 PredOp(mnem, _machInst, __opClass), 236 dest(_dest), op1(_op1), op2(_op2) 237 {} 238 239 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 240}; 241 242class RegRegImmOp : public PredOp 243{ 244 protected: 245 IntRegIndex dest; 246 IntRegIndex op1; 247 uint64_t imm; 248 249 RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 250 IntRegIndex _dest, IntRegIndex _op1, 251 uint64_t _imm) : 252 PredOp(mnem, _machInst, __opClass), 253 dest(_dest), op1(_op1), imm(_imm) 254 {} 255 256 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 257}; 258 259class RegImmImmOp : public PredOp 260{ 261 protected: 262 IntRegIndex dest; 263 IntRegIndex op1; 264 uint64_t imm1; 265 uint64_t imm2; 266 267 RegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 268 IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2) : 269 PredOp(mnem, _machInst, __opClass), 270 dest(_dest), imm1(_imm1), imm2(_imm2) 271 {} 272 273 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 274}; 275 276class RegRegImmImmOp : public PredOp 277{ 278 protected: 279 IntRegIndex dest; 280 IntRegIndex op1; 281 uint64_t imm1; 282 uint64_t imm2; 283 284 RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 285 IntRegIndex _dest, IntRegIndex _op1, 286 uint64_t _imm1, uint64_t _imm2) : 287 PredOp(mnem, _machInst, __opClass), 288 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 289 {} 290 291 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 292}; 293 294class RegImmRegShiftOp : public PredOp 295{ 296 protected: 297 IntRegIndex dest; 298 uint64_t imm; 299 IntRegIndex op1; 300 int32_t shiftAmt; 301 ArmShiftType shiftType; 302 303 RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 304 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, 305 int32_t _shiftAmt, ArmShiftType _shiftType) : 306 PredOp(mnem, _machInst, __opClass), 307 dest(_dest), imm(_imm), op1(_op1), 308 shiftAmt(_shiftAmt), shiftType(_shiftType) 309 {} 310 311 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 312}; 313 314class UnknownOp : public PredOp 315{ 316 protected: 317 318 UnknownOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 319 PredOp(mnem, _machInst, __opClass) 320 {} 321 322 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 323}; 324 325#endif 326