misc.cc revision 12104:edd63f9c6184 
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/arm/insts/misc.hh"
42
43#include "cpu/reg_class.hh"
44
45std::string
46MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
47{
48    std::stringstream ss;
49    printMnemonic(ss);
50    printIntReg(ss, dest);
51    ss << ", ";
52    bool foundPsr = false;
53    for (unsigned i = 0; i < numSrcRegs(); i++) {
54        RegId reg = srcRegIdx(i);
55        if (reg.regClass != MiscRegClass) {
56            continue;
57        }
58        if (reg.regIdx == MISCREG_CPSR) {
59            ss << "cpsr";
60            foundPsr = true;
61            break;
62        }
63        if (reg.regIdx == MISCREG_SPSR) {
64            ss << "spsr";
65            foundPsr = true;
66            break;
67        }
68    }
69    if (!foundPsr) {
70        ss << "????";
71    }
72    return ss.str();
73}
74
75void
76MsrBase::printMsrBase(std::ostream &os) const
77{
78    printMnemonic(os);
79    bool apsr = false;
80    bool foundPsr = false;
81    for (unsigned i = 0; i < numDestRegs(); i++) {
82        RegId reg = destRegIdx(i);
83        if (reg.regClass != MiscRegClass) {
84            continue;
85        }
86        if (reg.regIdx == MISCREG_CPSR) {
87            os << "cpsr_";
88            foundPsr = true;
89            break;
90        }
91        if (reg.regIdx == MISCREG_SPSR) {
92            if (bits(byteMask, 1, 0)) {
93                os << "spsr_";
94            } else {
95                os << "apsr_";
96                apsr = true;
97            }
98            foundPsr = true;
99            break;
100        }
101    }
102    if (!foundPsr) {
103        os << "????";
104        return;
105    }
106    if (bits(byteMask, 3)) {
107        if (apsr) {
108            os << "nzcvq";
109        } else {
110            os << "f";
111        }
112    }
113    if (bits(byteMask, 2)) {
114        if (apsr) {
115            os << "g";
116        } else {
117            os << "s";
118        }
119    }
120    if (bits(byteMask, 1)) {
121        os << "x";
122    }
123    if (bits(byteMask, 0)) {
124        os << "c";
125    }
126}
127
128std::string
129MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
130{
131    std::stringstream ss;
132    printMsrBase(ss);
133    ccprintf(ss, ", #%#x", imm);
134    return ss.str();
135}
136
137std::string
138MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
139{
140    std::stringstream ss;
141    printMsrBase(ss);
142    ss << ", ";
143    printIntReg(ss, op1);
144    return ss.str();
145}
146
147std::string
148MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
149{
150    std::stringstream ss;
151    printMnemonic(ss);
152    printIntReg(ss, dest);
153    ss << ", ";
154    printIntReg(ss, dest2);
155    ss << ", ";
156    printIntReg(ss, op1);
157    return ss.str();
158}
159
160std::string
161McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
162{
163    std::stringstream ss;
164    printMnemonic(ss);
165    printIntReg(ss, dest);
166    ss << ", ";
167    printIntReg(ss, op1);
168    ss << ", ";
169    printIntReg(ss, op2);
170    return ss.str();
171}
172
173std::string
174ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
175{
176    std::stringstream ss;
177    printMnemonic(ss);
178    ccprintf(ss, "#%d", imm);
179    return ss.str();
180}
181
182std::string
183RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
184{
185    std::stringstream ss;
186    printMnemonic(ss);
187    printIntReg(ss, dest);
188    ccprintf(ss, ", #%d", imm);
189    return ss.str();
190}
191
192std::string
193RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
194{
195    std::stringstream ss;
196    printMnemonic(ss);
197    printIntReg(ss, dest);
198    ss << ", ";
199    printIntReg(ss, op1);
200    return ss.str();
201}
202
203std::string
204RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
205{
206    std::stringstream ss;
207    printMnemonic(ss);
208    printIntReg(ss, dest);
209    ss << ", ";
210    printIntReg(ss, op1);
211    ss << ", ";
212    printIntReg(ss, op2);
213    ccprintf(ss, ", #%d", imm);
214    return ss.str();
215}
216
217std::string
218RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
219{
220    std::stringstream ss;
221    printMnemonic(ss);
222    printIntReg(ss, dest);
223    ss << ", ";
224    printIntReg(ss, op1);
225    ss << ", ";
226    printIntReg(ss, op2);
227    ss << ", ";
228    printIntReg(ss, op3);
229    return ss.str();
230}
231
232std::string
233RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
234{
235    std::stringstream ss;
236    printMnemonic(ss);
237    printIntReg(ss, dest);
238    ss << ", ";
239    printIntReg(ss, op1);
240    ss << ", ";
241    printIntReg(ss, op2);
242    return ss.str();
243}
244
245std::string
246RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
247{
248    std::stringstream ss;
249    printMnemonic(ss);
250    printIntReg(ss, dest);
251    ss << ", ";
252    printIntReg(ss, op1);
253    ccprintf(ss, ", #%d", imm);
254    return ss.str();
255}
256
257std::string
258MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
259{
260    std::stringstream ss;
261    printMnemonic(ss);
262    printIntReg(ss, dest);
263    ss << ", ";
264    printIntReg(ss, op1);
265    ccprintf(ss, ", #%d", imm);
266    return ss.str();
267}
268
269std::string
270RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
271{
272    std::stringstream ss;
273    printMnemonic(ss);
274    printIntReg(ss, dest);
275    ss << ", ";
276    printIntReg(ss, op1);
277    ccprintf(ss, ", #%d", imm);
278    return ss.str();
279}
280
281std::string
282RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
283{
284    std::stringstream ss;
285    printMnemonic(ss);
286    printIntReg(ss, dest);
287    ccprintf(ss, ", #%d, #%d", imm1, imm2);
288    return ss.str();
289}
290
291std::string
292RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
293{
294    std::stringstream ss;
295    printMnemonic(ss);
296    printIntReg(ss, dest);
297    ss << ", ";
298    printIntReg(ss, op1);
299    ccprintf(ss, ", #%d, #%d", imm1, imm2);
300    return ss.str();
301}
302
303std::string
304RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
305{
306    std::stringstream ss;
307    printMnemonic(ss);
308    printIntReg(ss, dest);
309    ccprintf(ss, ", #%d, ", imm);
310    printIntReg(ss, op1);
311    return ss.str();
312}
313
314std::string
315RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
316{
317    std::stringstream ss;
318    printMnemonic(ss);
319    printIntReg(ss, dest);
320    ccprintf(ss, ", #%d, ", imm);
321    printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
322    printIntReg(ss, op1);
323    return ss.str();
324}
325
326std::string
327UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
328{
329    return csprintf("%-10s (inst %#08x)", "unknown", machInst);
330}
331