misc.cc revision 11793:ef606668d247 
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/arm/insts/misc.hh"
42
43#include "cpu/reg_class.hh"
44
45std::string
46MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
47{
48    std::stringstream ss;
49    printMnemonic(ss);
50    printReg(ss, dest);
51    ss << ", ";
52    bool foundPsr = false;
53    for (unsigned i = 0; i < numSrcRegs(); i++) {
54        RegIndex idx = srcRegIdx(i);
55        RegIndex rel_idx;
56        if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
57            continue;
58        }
59        if (rel_idx == MISCREG_CPSR) {
60            ss << "cpsr";
61            foundPsr = true;
62            break;
63        }
64        if (rel_idx == MISCREG_SPSR) {
65            ss << "spsr";
66            foundPsr = true;
67            break;
68        }
69    }
70    if (!foundPsr) {
71        ss << "????";
72    }
73    return ss.str();
74}
75
76void
77MsrBase::printMsrBase(std::ostream &os) const
78{
79    printMnemonic(os);
80    bool apsr = false;
81    bool foundPsr = false;
82    for (unsigned i = 0; i < numDestRegs(); i++) {
83        int idx = destRegIdx(i);
84        if (idx < Misc_Reg_Base) {
85            continue;
86        }
87        idx -= Misc_Reg_Base;
88        if (idx == MISCREG_CPSR) {
89            os << "cpsr_";
90            foundPsr = true;
91            break;
92        }
93        if (idx == MISCREG_SPSR) {
94            if (bits(byteMask, 1, 0)) {
95                os << "spsr_";
96            } else {
97                os << "apsr_";
98                apsr = true;
99            }
100            foundPsr = true;
101            break;
102        }
103    }
104    if (!foundPsr) {
105        os << "????";
106        return;
107    }
108    if (bits(byteMask, 3)) {
109        if (apsr) {
110            os << "nzcvq";
111        } else {
112            os << "f";
113        }
114    }
115    if (bits(byteMask, 2)) {
116        if (apsr) {
117            os << "g";
118        } else {
119            os << "s";
120        }
121    }
122    if (bits(byteMask, 1)) {
123        os << "x";
124    }
125    if (bits(byteMask, 0)) {
126        os << "c";
127    }
128}
129
130std::string
131MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
132{
133    std::stringstream ss;
134    printMsrBase(ss);
135    ccprintf(ss, ", #%#x", imm);
136    return ss.str();
137}
138
139std::string
140MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
141{
142    std::stringstream ss;
143    printMsrBase(ss);
144    ss << ", ";
145    printReg(ss, op1);
146    return ss.str();
147}
148
149std::string
150MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
151{
152    std::stringstream ss;
153    printMnemonic(ss);
154    printReg(ss, dest);
155    ss << ", ";
156    printReg(ss, dest2);
157    ss << ", ";
158    printReg(ss, op1);
159    return ss.str();
160}
161
162std::string
163McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
164{
165    std::stringstream ss;
166    printMnemonic(ss);
167    printReg(ss, dest);
168    ss << ", ";
169    printReg(ss, op1);
170    ss << ", ";
171    printReg(ss, op2);
172    return ss.str();
173}
174
175std::string
176ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
177{
178    std::stringstream ss;
179    printMnemonic(ss);
180    ccprintf(ss, "#%d", imm);
181    return ss.str();
182}
183
184std::string
185RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
186{
187    std::stringstream ss;
188    printMnemonic(ss);
189    printReg(ss, dest);
190    ccprintf(ss, ", #%d", imm);
191    return ss.str();
192}
193
194std::string
195RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
196{
197    std::stringstream ss;
198    printMnemonic(ss);
199    printReg(ss, dest);
200    ss << ", ";
201    printReg(ss, op1);
202    return ss.str();
203}
204
205std::string
206RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
207{
208    std::stringstream ss;
209    printMnemonic(ss);
210    printReg(ss, dest);
211    ss << ", ";
212    printReg(ss, op1);
213    ss << ", ";
214    printReg(ss, op2);
215    ccprintf(ss, ", #%d", imm);
216    return ss.str();
217}
218
219std::string
220RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
221{
222    std::stringstream ss;
223    printMnemonic(ss);
224    printReg(ss, dest);
225    ss << ", ";
226    printReg(ss, op1);
227    ss << ", ";
228    printReg(ss, op2);
229    ss << ", ";
230    printReg(ss, op3);
231    return ss.str();
232}
233
234std::string
235RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
236{
237    std::stringstream ss;
238    printMnemonic(ss);
239    printReg(ss, dest);
240    ss << ", ";
241    printReg(ss, op1);
242    ss << ", ";
243    printReg(ss, op2);
244    return ss.str();
245}
246
247std::string
248RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
249{
250    std::stringstream ss;
251    printMnemonic(ss);
252    printReg(ss, dest);
253    ss << ", ";
254    printReg(ss, op1);
255    ccprintf(ss, ", #%d", imm);
256    return ss.str();
257}
258
259std::string
260MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
261{
262    std::stringstream ss;
263    printMnemonic(ss);
264    printReg(ss, dest);
265    ss << ", ";
266    printReg(ss, op1);
267    ccprintf(ss, ", #%d", imm);
268    return ss.str();
269}
270
271std::string
272RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
273{
274    std::stringstream ss;
275    printMnemonic(ss);
276    printReg(ss, dest);
277    ss << ", ";
278    printReg(ss, op1);
279    ccprintf(ss, ", #%d", imm);
280    return ss.str();
281}
282
283std::string
284RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
285{
286    std::stringstream ss;
287    printMnemonic(ss);
288    printReg(ss, dest);
289    ccprintf(ss, ", #%d, #%d", imm1, imm2);
290    return ss.str();
291}
292
293std::string
294RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
295{
296    std::stringstream ss;
297    printMnemonic(ss);
298    printReg(ss, dest);
299    ss << ", ";
300    printReg(ss, op1);
301    ccprintf(ss, ", #%d, #%d", imm1, imm2);
302    return ss.str();
303}
304
305std::string
306RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
307{
308    std::stringstream ss;
309    printMnemonic(ss);
310    printReg(ss, dest);
311    ccprintf(ss, ", #%d, ", imm);
312    printReg(ss, op1);
313    return ss.str();
314}
315
316std::string
317RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
318{
319    std::stringstream ss;
320    printMnemonic(ss);
321    printReg(ss, dest);
322    ccprintf(ss, ", #%d, ", imm);
323    printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
324    printReg(ss, op1);
325    return ss.str();
326}
327
328std::string
329UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
330{
331    return csprintf("%-10s (inst %#08x)", "unknown", machInst);
332}
333