mem64.hh revision 12616:4b463b4dc098 
1/*
2 * Copyright (c) 2011-2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39#ifndef __ARCH_ARM_MEM64_HH__
40#define __ARCH_ARM_MEM64_HH__
41
42#include "arch/arm/insts/static_inst.hh"
43
44namespace ArmISA
45{
46
47class SysDC64 : public ArmStaticInst
48{
49  protected:
50    IntRegIndex base;
51    IntRegIndex dest;
52    uint64_t imm;
53
54    SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
55            IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm)
56        : ArmStaticInst(mnem, _machInst, __opClass), base(_base),
57          dest((IntRegIndex)miscReg), imm(_imm)
58    {}
59    std::string generateDisassembly(
60            Addr pc, const SymbolTable *symtab) const override;
61};
62
63class MightBeMicro64 : public ArmStaticInst
64{
65  protected:
66    MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
67        : ArmStaticInst(mnem, _machInst, __opClass)
68    {}
69
70    void
71    advancePC(PCState &pcState) const
72    {
73        if (flags[IsLastMicroop]) {
74            pcState.uEnd();
75        } else if (flags[IsMicroop]) {
76            pcState.uAdvance();
77        } else {
78            pcState.advance();
79        }
80    }
81};
82
83class Memory64 : public MightBeMicro64
84{
85  public:
86    enum AddrMode {
87        AddrMd_Offset,
88        AddrMd_PreIndex,
89        AddrMd_PostIndex
90    };
91
92  protected:
93
94    IntRegIndex dest;
95    IntRegIndex base;
96    /// True if the base register is SP (used for SP alignment checking).
97    bool baseIsSP;
98    static const unsigned numMicroops = 3;
99
100    StaticInstPtr *uops;
101
102    Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
103             IntRegIndex _dest, IntRegIndex _base)
104        : MightBeMicro64(mnem, _machInst, __opClass),
105          dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
106    {
107        baseIsSP = isSP(_base);
108    }
109
110    virtual
111    ~Memory64()
112    {
113        delete [] uops;
114    }
115
116    StaticInstPtr
117    fetchMicroop(MicroPC microPC) const override
118    {
119        assert(uops != NULL && microPC < numMicroops);
120        return uops[microPC];
121    }
122
123    void startDisassembly(std::ostream &os) const;
124
125    unsigned memAccessFlags;
126
127    void setExcAcRel(bool exclusive, bool acrel);
128};
129
130class MemoryImm64 : public Memory64
131{
132  protected:
133    int64_t imm;
134
135    MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
136                IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
137        : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
138    {}
139
140    std::string generateDisassembly(
141            Addr pc, const SymbolTable *symtab) const override;
142};
143
144class MemoryDImm64 : public MemoryImm64
145{
146  protected:
147    IntRegIndex dest2;
148
149    MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
150                IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
151                int64_t _imm)
152        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
153          dest2(_dest2)
154    {}
155
156    std::string generateDisassembly(
157            Addr pc, const SymbolTable *symtab) const override;
158};
159
160class MemoryDImmEx64 : public MemoryDImm64
161{
162  protected:
163    IntRegIndex result;
164
165    MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
166                 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
167                 IntRegIndex _base, int32_t _imm)
168        : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
169                     _base, _imm), result(_result)
170    {}
171
172    std::string generateDisassembly(
173            Addr pc, const SymbolTable *symtab) const override;
174};
175
176class MemoryPreIndex64 : public MemoryImm64
177{
178  protected:
179    MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
180                     OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
181                     int64_t _imm)
182        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
183    {}
184
185    std::string generateDisassembly(
186            Addr pc, const SymbolTable *symtab) const override;
187};
188
189class MemoryPostIndex64 : public MemoryImm64
190{
191  protected:
192    MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
193                      OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
194                      int64_t _imm)
195        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
196    {}
197
198    std::string generateDisassembly(
199            Addr pc, const SymbolTable *symtab) const override;
200};
201
202class MemoryReg64 : public Memory64
203{
204  protected:
205    IntRegIndex offset;
206    ArmExtendType type;
207    uint64_t shiftAmt;
208
209    MemoryReg64(const char *mnem, ExtMachInst _machInst,
210                OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
211                IntRegIndex _offset, ArmExtendType _type,
212                uint64_t _shiftAmt)
213        : Memory64(mnem, _machInst, __opClass, _dest, _base),
214          offset(_offset), type(_type), shiftAmt(_shiftAmt)
215    {}
216
217    std::string generateDisassembly(
218            Addr pc, const SymbolTable *symtab) const override;
219};
220
221class MemoryRaw64 : public Memory64
222{
223  protected:
224    MemoryRaw64(const char *mnem, ExtMachInst _machInst,
225                OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
226        : Memory64(mnem, _machInst, __opClass, _dest, _base)
227    {}
228
229    std::string generateDisassembly(
230            Addr pc, const SymbolTable *symtab) const override;
231};
232
233class MemoryEx64 : public Memory64
234{
235  protected:
236    IntRegIndex result;
237
238    MemoryEx64(const char *mnem, ExtMachInst _machInst,
239               OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
240               IntRegIndex _result)
241        : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
242    {}
243
244    std::string generateDisassembly(
245            Addr pc, const SymbolTable *symtab) const override;
246};
247
248class MemoryLiteral64 : public Memory64
249{
250  protected:
251    int64_t imm;
252
253    MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
254                    OpClass __opClass, IntRegIndex _dest, int64_t _imm)
255        : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
256    {}
257
258    std::string generateDisassembly(
259            Addr pc, const SymbolTable *symtab) const override;
260};
261}
262
263#endif //__ARCH_ARM_INSTS_MEM_HH__
264