mem.hh revision 7646:a444dbee8c07
18706Sandreas.hansson@arm.com/* 27586SAli.Saidi@arm.com * Copyright (c) 2010 ARM Limited 37586SAli.Saidi@arm.com * All rights reserved 47586SAli.Saidi@arm.com * 57586SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67586SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77586SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87586SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97586SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107586SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117586SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127586SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137905SBrad.Beckmann@amd.com * 145323Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 152934Sktlim@umich.edu * All rights reserved. 162934Sktlim@umich.edu * 172934Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu * this software without specific prior written permission. 272934Sktlim@umich.edu * 282934Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu * 402934Sktlim@umich.edu * Authors: Stephen Hines 412934Sktlim@umich.edu */ 422934Sktlim@umich.edu#ifndef __ARCH_ARM_MEM_HH__ 432995Ssaidi@eecs.umich.edu#define __ARCH_ARM_MEM_HH__ 448528SAli.Saidi@ARM.com 452934Sktlim@umich.edu#include "arch/arm/insts/pred_inst.hh" 462934Sktlim@umich.edu 472934Sktlim@umich.edunamespace ArmISA 482934Sktlim@umich.edu{ 492934Sktlim@umich.edu 502934Sktlim@umich.educlass Swap : public PredOp 512934Sktlim@umich.edu{ 522934Sktlim@umich.edu protected: 539036Sandreas.hansson@arm.com IntRegIndex dest; 546122SSteve.Reinhardt@amd.com IntRegIndex op1; 556122SSteve.Reinhardt@amd.com IntRegIndex base; 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 584520Ssaidi@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base) 598713Sandreas.hansson@arm.com : PredOp(mnem, _machInst, __opClass), 604520Ssaidi@eecs.umich.edu dest(_dest), op1(_op1), base(_base) 614982Ssaidi@eecs.umich.edu {} 624520Ssaidi@eecs.umich.edu 634520Ssaidi@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 642934Sktlim@umich.edu}; 652934Sktlim@umich.edu 663005Sstever@eecs.umich.edu// The address is a base register plus an immediate. 673005Sstever@eecs.umich.educlass RfeOp : public PredOp 683304Sstever@eecs.umich.edu{ 692995Ssaidi@eecs.umich.edu public: 709036Sandreas.hansson@arm.com enum AddrMode { 719036Sandreas.hansson@arm.com DecrementAfter, 728713Sandreas.hansson@arm.com DecrementBefore, 738713Sandreas.hansson@arm.com IncrementAfter, 749164Sandreas.hansson@arm.com IncrementBefore 758713Sandreas.hansson@arm.com }; 768931Sandreas.hansson@arm.com protected: 778839Sandreas.hansson@arm.com IntRegIndex base; 788839Sandreas.hansson@arm.com AddrMode mode; 798839Sandreas.hansson@arm.com bool wb; 802934Sktlim@umich.edu static const unsigned numMicroops = 2; 812934Sktlim@umich.edu 822995Ssaidi@eecs.umich.edu StaticInstPtr *uops; 832934Sktlim@umich.edu 842934Sktlim@umich.edu RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 852934Sktlim@umich.edu IntRegIndex _base, AddrMode _mode, bool _wb) 868839Sandreas.hansson@arm.com : PredOp(mnem, _machInst, __opClass), 878839Sandreas.hansson@arm.com base(_base), mode(_mode), wb(_wb), uops(NULL) 888839Sandreas.hansson@arm.com {} 898839Sandreas.hansson@arm.com 908839Sandreas.hansson@arm.com virtual 918839Sandreas.hansson@arm.com ~RfeOp() 922995Ssaidi@eecs.umich.edu { 932934Sktlim@umich.edu delete uops; 942934Sktlim@umich.edu } 952953Sktlim@umich.edu 965478Snate@binkert.org StaticInstPtr 972934Sktlim@umich.edu fetchMicroop(MicroPC microPC) 983449Shsul@eecs.umich.edu { 992934Sktlim@umich.edu assert(uops != NULL && microPC < numMicroops); 1002934Sktlim@umich.edu return uops[microPC]; 1012934Sktlim@umich.edu } 1028839Sandreas.hansson@arm.com 1038706Sandreas.hansson@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1042934Sktlim@umich.edu}; 1052934Sktlim@umich.edu 1067014SBrad.Beckmann@amd.com// The address is a base register plus an immediate. 1076765SBrad.Beckmann@amd.comclass SrsOp : public PredOp 1086765SBrad.Beckmann@amd.com{ 1096765SBrad.Beckmann@amd.com public: 1106765SBrad.Beckmann@amd.com enum AddrMode { 1116765SBrad.Beckmann@amd.com DecrementAfter, 1128931Sandreas.hansson@arm.com DecrementBefore, 1137014SBrad.Beckmann@amd.com IncrementAfter, 1146765SBrad.Beckmann@amd.com IncrementBefore 1156765SBrad.Beckmann@amd.com }; 1166765SBrad.Beckmann@amd.com protected: 1176765SBrad.Beckmann@amd.com uint32_t regMode; 1186765SBrad.Beckmann@amd.com AddrMode mode; 1196765SBrad.Beckmann@amd.com bool wb; 1209036Sandreas.hansson@arm.com static const unsigned numMicroops = 2; 1216893SBrad.Beckmann@amd.com 1226893SBrad.Beckmann@amd.com StaticInstPtr *uops; 1236893SBrad.Beckmann@amd.com 1246893SBrad.Beckmann@amd.com SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1256893SBrad.Beckmann@amd.com uint32_t _regMode, AddrMode _mode, bool _wb) 1266893SBrad.Beckmann@amd.com : PredOp(mnem, _machInst, __opClass), 1278898Snilay@cs.wisc.edu regMode(_regMode), mode(_mode), wb(_wb), uops(NULL) 1286893SBrad.Beckmann@amd.com {} 1296765SBrad.Beckmann@amd.com 1306765SBrad.Beckmann@amd.com virtual 1316765SBrad.Beckmann@amd.com ~SrsOp() 1326765SBrad.Beckmann@amd.com { 1336765SBrad.Beckmann@amd.com delete uops; 1346765SBrad.Beckmann@amd.com } 1358839Sandreas.hansson@arm.com 1368839Sandreas.hansson@arm.com StaticInstPtr 1378839Sandreas.hansson@arm.com fetchMicroop(MicroPC microPC) 1388839Sandreas.hansson@arm.com { 1396765SBrad.Beckmann@amd.com assert(uops != NULL && microPC < numMicroops); 1406893SBrad.Beckmann@amd.com return uops[microPC]; 1417633SBrad.Beckmann@amd.com } 1427633SBrad.Beckmann@amd.com 1436893SBrad.Beckmann@amd.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1448929Snilay@cs.wisc.edu}; 1456765SBrad.Beckmann@amd.com 1466765SBrad.Beckmann@amd.comclass Memory : public PredOp 1476765SBrad.Beckmann@amd.com{ 1486765SBrad.Beckmann@amd.com public: 1496765SBrad.Beckmann@amd.com enum AddrMode { 1506765SBrad.Beckmann@amd.com AddrMd_Offset, 1516765SBrad.Beckmann@amd.com AddrMd_PreIndex, 1526765SBrad.Beckmann@amd.com AddrMd_PostIndex 1536765SBrad.Beckmann@amd.com }; 1546765SBrad.Beckmann@amd.com 1556765SBrad.Beckmann@amd.com protected: 1566765SBrad.Beckmann@amd.com 1576765SBrad.Beckmann@amd.com IntRegIndex dest; 1583584Ssaidi@eecs.umich.edu IntRegIndex base; 1598713Sandreas.hansson@arm.com bool add; 1608713Sandreas.hansson@arm.com static const unsigned numMicroops = 3; 1618713Sandreas.hansson@arm.com 1628713Sandreas.hansson@arm.com StaticInstPtr *uops; 1634486Sbinkertn@umich.edu 1644486Sbinkertn@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1654486Sbinkertn@umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add) 1664486Sbinkertn@umich.edu : PredOp(mnem, _machInst, __opClass), 1674486Sbinkertn@umich.edu dest(_dest), base(_base), add(_add), uops(NULL) 1684486Sbinkertn@umich.edu {} 1694486Sbinkertn@umich.edu 1703584Ssaidi@eecs.umich.edu virtual 1713584Ssaidi@eecs.umich.edu ~Memory() 1723584Ssaidi@eecs.umich.edu { 1733584Ssaidi@eecs.umich.edu delete [] uops; 1743584Ssaidi@eecs.umich.edu } 1759036Sandreas.hansson@arm.com 1769036Sandreas.hansson@arm.com StaticInstPtr 1779164Sandreas.hansson@arm.com fetchMicroop(MicroPC microPC) 1783743Sgblack@eecs.umich.edu { 1794104Ssaidi@eecs.umich.edu assert(uops != NULL && microPC < numMicroops); 1803743Sgblack@eecs.umich.edu return uops[microPC]; 1818931Sandreas.hansson@arm.com } 1828931Sandreas.hansson@arm.com 1838931Sandreas.hansson@arm.com virtual void 1848931Sandreas.hansson@arm.com printOffset(std::ostream &os) const 1858839Sandreas.hansson@arm.com {} 1868839Sandreas.hansson@arm.com 1878839Sandreas.hansson@arm.com virtual void 1888839Sandreas.hansson@arm.com printDest(std::ostream &os) const 1898839Sandreas.hansson@arm.com { 1908839Sandreas.hansson@arm.com printReg(os, dest); 1918839Sandreas.hansson@arm.com } 1928839Sandreas.hansson@arm.com 1933584Ssaidi@eecs.umich.edu void printInst(std::ostream &os, AddrMode addrMode) const; 1943898Ssaidi@eecs.umich.edu}; 1953898Ssaidi@eecs.umich.edu 1968839Sandreas.hansson@arm.com// The address is a base register plus an immediate. 1978713Sandreas.hansson@arm.comclass MemoryImm : public Memory 1988713Sandreas.hansson@arm.com{ 1998713Sandreas.hansson@arm.com protected: 2008713Sandreas.hansson@arm.com int32_t imm; 2018713Sandreas.hansson@arm.com 2028713Sandreas.hansson@arm.com MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2038713Sandreas.hansson@arm.com IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) 2048713Sandreas.hansson@arm.com : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) 2058713Sandreas.hansson@arm.com {} 2068713Sandreas.hansson@arm.com 2078713Sandreas.hansson@arm.com void 2088713Sandreas.hansson@arm.com printOffset(std::ostream &os) const 2098713Sandreas.hansson@arm.com { 2108713Sandreas.hansson@arm.com int32_t pImm = imm; 2118713Sandreas.hansson@arm.com if (!add) 2128713Sandreas.hansson@arm.com pImm = -pImm; 2138713Sandreas.hansson@arm.com ccprintf(os, "#%d", pImm); 2148713Sandreas.hansson@arm.com } 2158713Sandreas.hansson@arm.com}; 2164103Ssaidi@eecs.umich.edu 2174103Ssaidi@eecs.umich.educlass MemoryExImm : public MemoryImm 2184103Ssaidi@eecs.umich.edu{ 2193745Sgblack@eecs.umich.edu protected: 2203745Sgblack@eecs.umich.edu IntRegIndex result; 2213745Sgblack@eecs.umich.edu 2223584Ssaidi@eecs.umich.edu MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2238839Sandreas.hansson@arm.com IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base, 2248706Sandreas.hansson@arm.com bool _add, int32_t _imm) 2253584Ssaidi@eecs.umich.edu : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 2263584Ssaidi@eecs.umich.edu result(_result) 2278061SAli.Saidi@ARM.com {} 2288061SAli.Saidi@ARM.com 2298061SAli.Saidi@ARM.com void 2307586SAli.Saidi@arm.com printDest(std::ostream &os) const 2317586SAli.Saidi@arm.com { 2327586SAli.Saidi@arm.com printReg(os, result); 2337586SAli.Saidi@arm.com os << ", "; 2347586SAli.Saidi@arm.com MemoryImm::printDest(os); 2357586SAli.Saidi@arm.com } 2367586SAli.Saidi@arm.com}; 2377586SAli.Saidi@arm.com 2387586SAli.Saidi@arm.com// The address is a base register plus an immediate. 2397586SAli.Saidi@arm.comclass MemoryDImm : public MemoryImm 2409036Sandreas.hansson@arm.com{ 2419036Sandreas.hansson@arm.com protected: 2427586SAli.Saidi@arm.com IntRegIndex dest2; 2439164Sandreas.hansson@arm.com 2448839Sandreas.hansson@arm.com MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2458839Sandreas.hansson@arm.com IntRegIndex _dest, IntRegIndex _dest2, 2467586SAli.Saidi@arm.com IntRegIndex _base, bool _add, int32_t _imm) 2477586SAli.Saidi@arm.com : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 2487586SAli.Saidi@arm.com dest2(_dest2) 2497586SAli.Saidi@arm.com {} 2507586SAli.Saidi@arm.com 2517586SAli.Saidi@arm.com void 2527586SAli.Saidi@arm.com printDest(std::ostream &os) const 2538525SAli.Saidi@ARM.com { 2548525SAli.Saidi@ARM.com MemoryImm::printDest(os); 2558870SAli.Saidi@ARM.com os << ", "; 2568870SAli.Saidi@ARM.com printReg(os, dest2); 2578870SAli.Saidi@ARM.com } 2587586SAli.Saidi@arm.com}; 2597586SAli.Saidi@arm.com 2607586SAli.Saidi@arm.comclass MemoryExDImm : public MemoryDImm 2617586SAli.Saidi@arm.com{ 2628528SAli.Saidi@ARM.com protected: 2638528SAli.Saidi@ARM.com IntRegIndex result; 2648528SAli.Saidi@ARM.com 2658528SAli.Saidi@ARM.com MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2668528SAli.Saidi@ARM.com IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, 2678528SAli.Saidi@ARM.com IntRegIndex _base, bool _add, int32_t _imm) 2688528SAli.Saidi@ARM.com : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2, 2698528SAli.Saidi@ARM.com _base, _add, _imm), result(_result) 2708528SAli.Saidi@ARM.com {} 2718061SAli.Saidi@ARM.com 2728061SAli.Saidi@ARM.com void 2738061SAli.Saidi@ARM.com printDest(std::ostream &os) const 2748931Sandreas.hansson@arm.com { 2758931Sandreas.hansson@arm.com printReg(os, result); 2768061SAli.Saidi@ARM.com os << ", "; 2778528SAli.Saidi@ARM.com MemoryDImm::printDest(os); 2787586SAli.Saidi@arm.com } 2798894Ssaidi@eecs.umich.edu}; 2808870SAli.Saidi@ARM.com 2818870SAli.Saidi@ARM.com// The address is a shifted register plus an immediate 2828870SAli.Saidi@ARM.comclass MemoryReg : public Memory 2838894Ssaidi@eecs.umich.edu{ 2848528SAli.Saidi@ARM.com protected: 2858212SAli.Saidi@ARM.com int32_t shiftAmt; 2868528SAli.Saidi@ARM.com ArmShiftType shiftType; 2878528SAli.Saidi@ARM.com IntRegIndex index; 2888931Sandreas.hansson@arm.com 2898931Sandreas.hansson@arm.com MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2908931Sandreas.hansson@arm.com IntRegIndex _dest, IntRegIndex _base, bool _add, 2918931Sandreas.hansson@arm.com int32_t _shiftAmt, ArmShiftType _shiftType, 2928870SAli.Saidi@ARM.com IntRegIndex _index) 2938528SAli.Saidi@ARM.com : Memory(mnem, _machInst, __opClass, _dest, _base, _add), 2948528SAli.Saidi@ARM.com shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) 2958287SAli.Saidi@ARM.com {} 2968643Satgutier@umich.edu 2978595SAli.Saidi@ARM.com void printOffset(std::ostream &os) const; 2988212SAli.Saidi@ARM.com}; 2997586SAli.Saidi@arm.com 3008839Sandreas.hansson@arm.comclass MemoryDReg : public MemoryReg 3018713Sandreas.hansson@arm.com{ 3027586SAli.Saidi@arm.com protected: 3037586SAli.Saidi@arm.com IntRegIndex dest2; 3047586SAli.Saidi@arm.com 3057949SAli.Saidi@ARM.com MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 3067586SAli.Saidi@arm.com IntRegIndex _dest, IntRegIndex _dest2, 3078839Sandreas.hansson@arm.com IntRegIndex _base, bool _add, 3088706Sandreas.hansson@arm.com int32_t _shiftAmt, ArmShiftType _shiftType, 3097586SAli.Saidi@arm.com IntRegIndex _index) 3107586SAli.Saidi@arm.com : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add, 3117586SAli.Saidi@arm.com _shiftAmt, _shiftType, _index), 3125222Sksewell@umich.edu dest2(_dest2) 3135222Sksewell@umich.edu {} 3145222Sksewell@umich.edu 3155222Sksewell@umich.edu void 3165222Sksewell@umich.edu printDest(std::ostream &os) const 3175222Sksewell@umich.edu { 3185222Sksewell@umich.edu MemoryReg::printDest(os); 3195222Sksewell@umich.edu os << ", "; 3205222Sksewell@umich.edu printReg(os, dest2); 3215222Sksewell@umich.edu } 3225222Sksewell@umich.edu}; 3239036Sandreas.hansson@arm.com 3249036Sandreas.hansson@arm.comtemplate<class Base> 3259164Sandreas.hansson@arm.comclass MemoryOffset : public Base 3268931Sandreas.hansson@arm.com{ 3278839Sandreas.hansson@arm.com protected: 3288839Sandreas.hansson@arm.com MemoryOffset(const char *mnem, ExtMachInst _machInst, 3298839Sandreas.hansson@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3305222Sksewell@umich.edu bool _add, int32_t _imm) 3315222Sksewell@umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3325222Sksewell@umich.edu {} 3335222Sksewell@umich.edu 3345222Sksewell@umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3355222Sksewell@umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3368839Sandreas.hansson@arm.com bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3378839Sandreas.hansson@arm.com IntRegIndex _index) 3388839Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3398839Sandreas.hansson@arm.com _shiftAmt, _shiftType, _index) 3408839Sandreas.hansson@arm.com {} 3418839Sandreas.hansson@arm.com 3425222Sksewell@umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3435222Sksewell@umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3445222Sksewell@umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3455222Sksewell@umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3465478Snate@binkert.org {} 3475222Sksewell@umich.edu 3485222Sksewell@umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3495222Sksewell@umich.edu OpClass __opClass, IntRegIndex _result, 3505222Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _dest2, 3518839Sandreas.hansson@arm.com IntRegIndex _base, bool _add, int32_t _imm) 3528706Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _result, 3535222Sksewell@umich.edu _dest, _dest2, _base, _add, _imm) 3545222Sksewell@umich.edu {} 3555323Sgblack@eecs.umich.edu 3565357Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3578323Ssteve.reinhardt@amd.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3585323Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3598858Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3608713Sandreas.hansson@arm.com IntRegIndex _index) 3618713Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3628713Sandreas.hansson@arm.com _shiftAmt, _shiftType, _index) 3638713Sandreas.hansson@arm.com {} 3648713Sandreas.hansson@arm.com 3658713Sandreas.hansson@arm.com std::string 3669036Sandreas.hansson@arm.com generateDisassembly(Addr pc, const SymbolTable *symtab) const 3678839Sandreas.hansson@arm.com { 3687905SBrad.Beckmann@amd.com std::stringstream ss; 3697905SBrad.Beckmann@amd.com this->printInst(ss, Memory::AddrMd_Offset); 3709036Sandreas.hansson@arm.com return ss.str(); 3719164Sandreas.hansson@arm.com } 3728839Sandreas.hansson@arm.com}; 3738839Sandreas.hansson@arm.com 3748713Sandreas.hansson@arm.comtemplate<class Base> 3758713Sandreas.hansson@arm.comclass MemoryPreIndex : public Base 3768713Sandreas.hansson@arm.com{ 3778713Sandreas.hansson@arm.com protected: 3788713Sandreas.hansson@arm.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3798713Sandreas.hansson@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3808713Sandreas.hansson@arm.com bool _add, int32_t _imm) 3818713Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3828713Sandreas.hansson@arm.com {} 3838713Sandreas.hansson@arm.com 3848713Sandreas.hansson@arm.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3858713Sandreas.hansson@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3868713Sandreas.hansson@arm.com bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3878713Sandreas.hansson@arm.com IntRegIndex _index) 3888713Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3898713Sandreas.hansson@arm.com _shiftAmt, _shiftType, _index) 3909164Sandreas.hansson@arm.com {} 3918839Sandreas.hansson@arm.com 3928839Sandreas.hansson@arm.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3938815Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3948815Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3958858Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3968858Sgblack@eecs.umich.edu {} 3977905SBrad.Beckmann@amd.com 3987905SBrad.Beckmann@amd.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3997905SBrad.Beckmann@amd.com OpClass __opClass, IntRegIndex _result, 4007905SBrad.Beckmann@amd.com IntRegIndex _dest, IntRegIndex _dest2, 4018839Sandreas.hansson@arm.com IntRegIndex _base, bool _add, int32_t _imm) 4028706Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _result, 4037905SBrad.Beckmann@amd.com _dest, _dest2, _base, _add, _imm) 4047905SBrad.Beckmann@amd.com {} 4059036Sandreas.hansson@arm.com 4067905SBrad.Beckmann@amd.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4077905SBrad.Beckmann@amd.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4087905SBrad.Beckmann@amd.com IntRegIndex _base, bool _add, 4097905SBrad.Beckmann@amd.com int32_t _shiftAmt, ArmShiftType _shiftType, 4107905SBrad.Beckmann@amd.com IntRegIndex _index) 4117905SBrad.Beckmann@amd.com : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 4128839Sandreas.hansson@arm.com _shiftAmt, _shiftType, _index) 4138929Snilay@cs.wisc.edu {} 4148929Snilay@cs.wisc.edu 4158929Snilay@cs.wisc.edu std::string 4168929Snilay@cs.wisc.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 4177905SBrad.Beckmann@amd.com { 4187905SBrad.Beckmann@amd.com std::stringstream ss; 4197905SBrad.Beckmann@amd.com this->printInst(ss, Memory::AddrMd_PreIndex); 4205613Sgblack@eecs.umich.edu return ss.str(); 4215613Sgblack@eecs.umich.edu } 4225613Sgblack@eecs.umich.edu}; 4235133Sgblack@eecs.umich.edu 4245133Sgblack@eecs.umich.edutemplate<class Base> 4255133Sgblack@eecs.umich.educlass MemoryPostIndex : public Base 4265133Sgblack@eecs.umich.edu{ 4275133Sgblack@eecs.umich.edu protected: 4286802Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4296802Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4305133Sgblack@eecs.umich.edu bool _add, int32_t _imm) 4318931Sandreas.hansson@arm.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 4325613Sgblack@eecs.umich.edu {} 4335613Sgblack@eecs.umich.edu 4345638Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4357905SBrad.Beckmann@amd.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4367905SBrad.Beckmann@amd.com bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 4377905SBrad.Beckmann@amd.com IntRegIndex _index) 4387905SBrad.Beckmann@amd.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, 4397905SBrad.Beckmann@amd.com _shiftAmt, _shiftType, _index) 4408858Sgblack@eecs.umich.edu {} 4415613Sgblack@eecs.umich.edu 4425613Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4435613Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4445841Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4455841Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 4465841Sgblack@eecs.umich.edu {} 4475841Sgblack@eecs.umich.edu 4485841Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4495841Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 4505841Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 4515615Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4525615Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 4535615Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 4545615Sgblack@eecs.umich.edu {} 4555641Sgblack@eecs.umich.edu 4568323Ssteve.reinhardt@amd.com MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4578323Ssteve.reinhardt@amd.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4586135Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 4596135Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 4606135Sgblack@eecs.umich.edu IntRegIndex _index) 4616135Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 4626135Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4636135Sgblack@eecs.umich.edu {} 4648323Ssteve.reinhardt@amd.com 4655644Sgblack@eecs.umich.edu std::string 4666135Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 4675644Sgblack@eecs.umich.edu { 4685644Sgblack@eecs.umich.edu std::stringstream ss; 4695644Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PostIndex); 4706135Sgblack@eecs.umich.edu return ss.str(); 4718323Ssteve.reinhardt@amd.com } 4725644Sgblack@eecs.umich.edu}; 4738323Ssteve.reinhardt@amd.com} 4745843Sgblack@eecs.umich.edu 4758323Ssteve.reinhardt@amd.com#endif //__ARCH_ARM_INSTS_MEM_HH__ 4765843Sgblack@eecs.umich.edu