mem.hh revision 7291
17118Sgblack@eecs.umich.edu/* 27118Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37118Sgblack@eecs.umich.edu * All rights reserved 47118Sgblack@eecs.umich.edu * 57118Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67118Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77118Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87118Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97118Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107118Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117118Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127118Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137118Sgblack@eecs.umich.edu * 147118Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MEM_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_MEM_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 466253Sgblack@eecs.umich.edu 476253Sgblack@eecs.umich.edunamespace ArmISA 486253Sgblack@eecs.umich.edu{ 497118Sgblack@eecs.umich.edu 507205Sgblack@eecs.umich.educlass Swap : public PredOp 517205Sgblack@eecs.umich.edu{ 527205Sgblack@eecs.umich.edu protected: 537205Sgblack@eecs.umich.edu IntRegIndex dest; 547205Sgblack@eecs.umich.edu IntRegIndex op1; 557205Sgblack@eecs.umich.edu IntRegIndex base; 567205Sgblack@eecs.umich.edu 577205Sgblack@eecs.umich.edu Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 587205Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base) 597205Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 607205Sgblack@eecs.umich.edu dest(_dest), op1(_op1), base(_base) 617205Sgblack@eecs.umich.edu {} 627205Sgblack@eecs.umich.edu 637205Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 647205Sgblack@eecs.umich.edu}; 657205Sgblack@eecs.umich.edu 667291Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 677291Sgblack@eecs.umich.educlass RfeOp : public PredOp 687291Sgblack@eecs.umich.edu{ 697291Sgblack@eecs.umich.edu public: 707291Sgblack@eecs.umich.edu enum AddrMode { 717291Sgblack@eecs.umich.edu DecrementAfter, 727291Sgblack@eecs.umich.edu DecrementBefore, 737291Sgblack@eecs.umich.edu IncrementAfter, 747291Sgblack@eecs.umich.edu IncrementBefore 757291Sgblack@eecs.umich.edu }; 767291Sgblack@eecs.umich.edu protected: 777291Sgblack@eecs.umich.edu IntRegIndex base; 787291Sgblack@eecs.umich.edu AddrMode mode; 797291Sgblack@eecs.umich.edu bool wb; 807291Sgblack@eecs.umich.edu 817291Sgblack@eecs.umich.edu RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 827291Sgblack@eecs.umich.edu IntRegIndex _base, AddrMode _mode, bool _wb) 837291Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 847291Sgblack@eecs.umich.edu base(_base), mode(_mode), wb(_wb) 857291Sgblack@eecs.umich.edu {} 867291Sgblack@eecs.umich.edu 877291Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 887291Sgblack@eecs.umich.edu}; 897291Sgblack@eecs.umich.edu 907132Sgblack@eecs.umich.educlass Memory : public PredOp 917118Sgblack@eecs.umich.edu{ 927118Sgblack@eecs.umich.edu public: 937118Sgblack@eecs.umich.edu enum AddrMode { 947118Sgblack@eecs.umich.edu AddrMd_Offset, 957118Sgblack@eecs.umich.edu AddrMd_PreIndex, 967118Sgblack@eecs.umich.edu AddrMd_PostIndex 977118Sgblack@eecs.umich.edu }; 987118Sgblack@eecs.umich.edu 997118Sgblack@eecs.umich.edu protected: 1007118Sgblack@eecs.umich.edu 1017118Sgblack@eecs.umich.edu IntRegIndex dest; 1027118Sgblack@eecs.umich.edu IntRegIndex base; 1037118Sgblack@eecs.umich.edu bool add; 1047118Sgblack@eecs.umich.edu 1057132Sgblack@eecs.umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1067132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add) 1077118Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 1087118Sgblack@eecs.umich.edu dest(_dest), base(_base), add(_add) 1097118Sgblack@eecs.umich.edu {} 1107118Sgblack@eecs.umich.edu 1117118Sgblack@eecs.umich.edu virtual void 1127118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 1137118Sgblack@eecs.umich.edu {} 1147118Sgblack@eecs.umich.edu 1157279Sgblack@eecs.umich.edu virtual void 1167279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 1177279Sgblack@eecs.umich.edu { 1187279Sgblack@eecs.umich.edu printReg(os, dest); 1197279Sgblack@eecs.umich.edu } 1207279Sgblack@eecs.umich.edu 1217118Sgblack@eecs.umich.edu void printInst(std::ostream &os, AddrMode addrMode) const; 1227118Sgblack@eecs.umich.edu}; 1237118Sgblack@eecs.umich.edu 1247118Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 1257132Sgblack@eecs.umich.educlass MemoryImm : public Memory 1267118Sgblack@eecs.umich.edu{ 1277118Sgblack@eecs.umich.edu protected: 1287118Sgblack@eecs.umich.edu int32_t imm; 1297118Sgblack@eecs.umich.edu 1307132Sgblack@eecs.umich.edu MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1317132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) 1327132Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) 1337118Sgblack@eecs.umich.edu {} 1347118Sgblack@eecs.umich.edu 1357118Sgblack@eecs.umich.edu void 1367118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 1377118Sgblack@eecs.umich.edu { 1387118Sgblack@eecs.umich.edu int32_t pImm = imm; 1397118Sgblack@eecs.umich.edu if (!add) 1407118Sgblack@eecs.umich.edu pImm = -pImm; 1417118Sgblack@eecs.umich.edu ccprintf(os, "#%d", pImm); 1427118Sgblack@eecs.umich.edu } 1437118Sgblack@eecs.umich.edu}; 1447118Sgblack@eecs.umich.edu 1457279Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 1467279Sgblack@eecs.umich.educlass MemoryDImm : public MemoryImm 1477279Sgblack@eecs.umich.edu{ 1487279Sgblack@eecs.umich.edu protected: 1497279Sgblack@eecs.umich.edu IntRegIndex dest2; 1507279Sgblack@eecs.umich.edu 1517279Sgblack@eecs.umich.edu MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1527279Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 1537279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 1547279Sgblack@eecs.umich.edu : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 1557279Sgblack@eecs.umich.edu dest2(_dest2) 1567279Sgblack@eecs.umich.edu {} 1577279Sgblack@eecs.umich.edu 1587279Sgblack@eecs.umich.edu void 1597279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 1607279Sgblack@eecs.umich.edu { 1617279Sgblack@eecs.umich.edu MemoryImm::printDest(os); 1627279Sgblack@eecs.umich.edu os << ", "; 1637279Sgblack@eecs.umich.edu printReg(os, dest2); 1647279Sgblack@eecs.umich.edu } 1657279Sgblack@eecs.umich.edu}; 1667279Sgblack@eecs.umich.edu 1677118Sgblack@eecs.umich.edu// The address is a shifted register plus an immediate 1687132Sgblack@eecs.umich.educlass MemoryReg : public Memory 1697118Sgblack@eecs.umich.edu{ 1707118Sgblack@eecs.umich.edu protected: 1717118Sgblack@eecs.umich.edu int32_t shiftAmt; 1727118Sgblack@eecs.umich.edu ArmShiftType shiftType; 1737118Sgblack@eecs.umich.edu IntRegIndex index; 1747118Sgblack@eecs.umich.edu 1757132Sgblack@eecs.umich.edu MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1767132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, 1777132Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 1787132Sgblack@eecs.umich.edu IntRegIndex _index) 1797132Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _dest, _base, _add), 1807118Sgblack@eecs.umich.edu shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) 1817118Sgblack@eecs.umich.edu {} 1827118Sgblack@eecs.umich.edu 1837118Sgblack@eecs.umich.edu void 1847118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 1857118Sgblack@eecs.umich.edu { 1867118Sgblack@eecs.umich.edu if (!add) 1877118Sgblack@eecs.umich.edu os << "-"; 1887118Sgblack@eecs.umich.edu printReg(os, index); 1897118Sgblack@eecs.umich.edu if (shiftType != LSL || shiftAmt != 0) { 1907118Sgblack@eecs.umich.edu switch (shiftType) { 1917118Sgblack@eecs.umich.edu case LSL: 1927118Sgblack@eecs.umich.edu ccprintf(os, " LSL #%d", shiftAmt); 1937118Sgblack@eecs.umich.edu break; 1947118Sgblack@eecs.umich.edu case LSR: 1957118Sgblack@eecs.umich.edu if (shiftAmt == 0) { 1967118Sgblack@eecs.umich.edu ccprintf(os, " LSR #%d", 32); 1977118Sgblack@eecs.umich.edu } else { 1987118Sgblack@eecs.umich.edu ccprintf(os, " LSR #%d", shiftAmt); 1997118Sgblack@eecs.umich.edu } 2007118Sgblack@eecs.umich.edu break; 2017118Sgblack@eecs.umich.edu case ASR: 2027118Sgblack@eecs.umich.edu if (shiftAmt == 0) { 2037118Sgblack@eecs.umich.edu ccprintf(os, " ASR #%d", 32); 2047118Sgblack@eecs.umich.edu } else { 2057118Sgblack@eecs.umich.edu ccprintf(os, " ASR #%d", shiftAmt); 2067118Sgblack@eecs.umich.edu } 2077118Sgblack@eecs.umich.edu break; 2087118Sgblack@eecs.umich.edu case ROR: 2097118Sgblack@eecs.umich.edu if (shiftAmt == 0) { 2107118Sgblack@eecs.umich.edu ccprintf(os, " RRX"); 2117118Sgblack@eecs.umich.edu } else { 2127118Sgblack@eecs.umich.edu ccprintf(os, " ROR #%d", shiftAmt); 2137118Sgblack@eecs.umich.edu } 2147118Sgblack@eecs.umich.edu break; 2157118Sgblack@eecs.umich.edu } 2167118Sgblack@eecs.umich.edu } 2177118Sgblack@eecs.umich.edu } 2187118Sgblack@eecs.umich.edu}; 2197118Sgblack@eecs.umich.edu 2207279Sgblack@eecs.umich.educlass MemoryDReg : public MemoryReg 2217279Sgblack@eecs.umich.edu{ 2227279Sgblack@eecs.umich.edu protected: 2237279Sgblack@eecs.umich.edu IntRegIndex dest2; 2247279Sgblack@eecs.umich.edu 2257279Sgblack@eecs.umich.edu MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2267279Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 2277279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 2287279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 2297279Sgblack@eecs.umich.edu IntRegIndex _index) 2307279Sgblack@eecs.umich.edu : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add, 2317279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index), 2327279Sgblack@eecs.umich.edu dest2(_dest2) 2337279Sgblack@eecs.umich.edu {} 2347279Sgblack@eecs.umich.edu 2357279Sgblack@eecs.umich.edu void 2367279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2377279Sgblack@eecs.umich.edu { 2387279Sgblack@eecs.umich.edu MemoryReg::printDest(os); 2397279Sgblack@eecs.umich.edu os << ", "; 2407279Sgblack@eecs.umich.edu printReg(os, dest2); 2417279Sgblack@eecs.umich.edu } 2427279Sgblack@eecs.umich.edu}; 2437279Sgblack@eecs.umich.edu 2447118Sgblack@eecs.umich.edutemplate<class Base> 2457132Sgblack@eecs.umich.educlass MemoryOffset : public Base 2467118Sgblack@eecs.umich.edu{ 2477118Sgblack@eecs.umich.edu protected: 2487132Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 2497132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2507132Sgblack@eecs.umich.edu bool _add, int32_t _imm) 2517132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 2527132Sgblack@eecs.umich.edu {} 2537132Sgblack@eecs.umich.edu 2547132Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 2557132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2567132Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 2577132Sgblack@eecs.umich.edu IntRegIndex _index) 2587132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 2597132Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 2607132Sgblack@eecs.umich.edu {} 2617132Sgblack@eecs.umich.edu 2627279Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 2637279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 2647279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 2657279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 2667279Sgblack@eecs.umich.edu {} 2677279Sgblack@eecs.umich.edu 2687279Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 2697279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 2707279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 2717279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 2727279Sgblack@eecs.umich.edu IntRegIndex _index) 2737279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 2747279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 2757279Sgblack@eecs.umich.edu {} 2767279Sgblack@eecs.umich.edu 2777132Sgblack@eecs.umich.edu std::string 2787132Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 2797132Sgblack@eecs.umich.edu { 2807132Sgblack@eecs.umich.edu std::stringstream ss; 2817132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_Offset); 2827132Sgblack@eecs.umich.edu return ss.str(); 2837132Sgblack@eecs.umich.edu } 2847132Sgblack@eecs.umich.edu}; 2857132Sgblack@eecs.umich.edu 2867132Sgblack@eecs.umich.edutemplate<class Base> 2877132Sgblack@eecs.umich.educlass MemoryPreIndex : public Base 2887132Sgblack@eecs.umich.edu{ 2897132Sgblack@eecs.umich.edu protected: 2907132Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 2917132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2927132Sgblack@eecs.umich.edu bool _add, int32_t _imm) 2937132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 2947132Sgblack@eecs.umich.edu {} 2957132Sgblack@eecs.umich.edu 2967132Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 2977132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2987132Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 2997132Sgblack@eecs.umich.edu IntRegIndex _index) 3007132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3017132Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3027132Sgblack@eecs.umich.edu {} 3037132Sgblack@eecs.umich.edu 3047279Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3057279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3067279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3077279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3087279Sgblack@eecs.umich.edu {} 3097279Sgblack@eecs.umich.edu 3107279Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3117279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3127279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3137279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3147279Sgblack@eecs.umich.edu IntRegIndex _index) 3157279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3167279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3177279Sgblack@eecs.umich.edu {} 3187279Sgblack@eecs.umich.edu 3197132Sgblack@eecs.umich.edu std::string 3207132Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 3217132Sgblack@eecs.umich.edu { 3227132Sgblack@eecs.umich.edu std::stringstream ss; 3237132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PreIndex); 3247132Sgblack@eecs.umich.edu return ss.str(); 3257132Sgblack@eecs.umich.edu } 3267132Sgblack@eecs.umich.edu}; 3277132Sgblack@eecs.umich.edu 3287132Sgblack@eecs.umich.edutemplate<class Base> 3297132Sgblack@eecs.umich.educlass MemoryPostIndex : public Base 3307132Sgblack@eecs.umich.edu{ 3317132Sgblack@eecs.umich.edu protected: 3327132Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3337118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3347118Sgblack@eecs.umich.edu bool _add, int32_t _imm) 3357118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3367118Sgblack@eecs.umich.edu {} 3377118Sgblack@eecs.umich.edu 3387132Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3397118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3407118Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3417118Sgblack@eecs.umich.edu IntRegIndex _index) 3427118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3437118Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3447118Sgblack@eecs.umich.edu {} 3457118Sgblack@eecs.umich.edu 3467279Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3477279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3487279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3497279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3507279Sgblack@eecs.umich.edu {} 3517279Sgblack@eecs.umich.edu 3527279Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3537279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3547279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3557279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3567279Sgblack@eecs.umich.edu IntRegIndex _index) 3577279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3587279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3597279Sgblack@eecs.umich.edu {} 3607279Sgblack@eecs.umich.edu 3617118Sgblack@eecs.umich.edu std::string 3627118Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 3637118Sgblack@eecs.umich.edu { 3647118Sgblack@eecs.umich.edu std::stringstream ss; 3657132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PostIndex); 3667118Sgblack@eecs.umich.edu return ss.str(); 3677118Sgblack@eecs.umich.edu } 3687118Sgblack@eecs.umich.edu}; 3696253Sgblack@eecs.umich.edu} 3706253Sgblack@eecs.umich.edu 3716253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MEM_HH__ 372