mem.hh revision 12616
17118Sgblack@eecs.umich.edu/* 27118Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37118Sgblack@eecs.umich.edu * All rights reserved 47118Sgblack@eecs.umich.edu * 57118Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67118Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77118Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87118Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97118Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107118Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117118Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127118Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137118Sgblack@eecs.umich.edu * 147118Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MEM_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_MEM_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 466253Sgblack@eecs.umich.edu 476253Sgblack@eecs.umich.edunamespace ArmISA 486253Sgblack@eecs.umich.edu{ 497118Sgblack@eecs.umich.edu 507205Sgblack@eecs.umich.educlass Swap : public PredOp 517205Sgblack@eecs.umich.edu{ 527205Sgblack@eecs.umich.edu protected: 537205Sgblack@eecs.umich.edu IntRegIndex dest; 547205Sgblack@eecs.umich.edu IntRegIndex op1; 557205Sgblack@eecs.umich.edu IntRegIndex base; 567205Sgblack@eecs.umich.edu 577205Sgblack@eecs.umich.edu Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 587205Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base) 597205Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 607205Sgblack@eecs.umich.edu dest(_dest), op1(_op1), base(_base) 617205Sgblack@eecs.umich.edu {} 627205Sgblack@eecs.umich.edu 6312616Sgabeblack@google.com std::string generateDisassembly( 6412616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 657205Sgblack@eecs.umich.edu}; 667205Sgblack@eecs.umich.edu 677720Sgblack@eecs.umich.educlass MightBeMicro : public PredOp 687720Sgblack@eecs.umich.edu{ 697720Sgblack@eecs.umich.edu protected: 707720Sgblack@eecs.umich.edu MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 717720Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass) 727720Sgblack@eecs.umich.edu {} 737720Sgblack@eecs.umich.edu 747720Sgblack@eecs.umich.edu void 757720Sgblack@eecs.umich.edu advancePC(PCState &pcState) const 767720Sgblack@eecs.umich.edu { 777720Sgblack@eecs.umich.edu if (flags[IsLastMicroop]) { 787720Sgblack@eecs.umich.edu pcState.uEnd(); 797720Sgblack@eecs.umich.edu } else if (flags[IsMicroop]) { 807720Sgblack@eecs.umich.edu pcState.uAdvance(); 817720Sgblack@eecs.umich.edu } else { 827720Sgblack@eecs.umich.edu pcState.advance(); 837720Sgblack@eecs.umich.edu } 847720Sgblack@eecs.umich.edu } 857720Sgblack@eecs.umich.edu}; 867720Sgblack@eecs.umich.edu 877291Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 887720Sgblack@eecs.umich.educlass RfeOp : public MightBeMicro 897291Sgblack@eecs.umich.edu{ 907291Sgblack@eecs.umich.edu public: 917291Sgblack@eecs.umich.edu enum AddrMode { 927291Sgblack@eecs.umich.edu DecrementAfter, 937291Sgblack@eecs.umich.edu DecrementBefore, 947291Sgblack@eecs.umich.edu IncrementAfter, 957291Sgblack@eecs.umich.edu IncrementBefore 967291Sgblack@eecs.umich.edu }; 977291Sgblack@eecs.umich.edu protected: 987291Sgblack@eecs.umich.edu IntRegIndex base; 997291Sgblack@eecs.umich.edu AddrMode mode; 1007291Sgblack@eecs.umich.edu bool wb; 1018140SMatt.Horsnell@arm.com IntRegIndex ura, urb, urc; 1028140SMatt.Horsnell@arm.com static const unsigned numMicroops = 3; 1037646Sgene.wu@arm.com 1047646Sgene.wu@arm.com StaticInstPtr *uops; 1057291Sgblack@eecs.umich.edu 1067291Sgblack@eecs.umich.edu RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1077291Sgblack@eecs.umich.edu IntRegIndex _base, AddrMode _mode, bool _wb) 1087720Sgblack@eecs.umich.edu : MightBeMicro(mnem, _machInst, __opClass), 1098140SMatt.Horsnell@arm.com base(_base), mode(_mode), wb(_wb), 1108140SMatt.Horsnell@arm.com ura(INTREG_UREG0), urb(INTREG_UREG1), 1118140SMatt.Horsnell@arm.com urc(INTREG_UREG2), 1128140SMatt.Horsnell@arm.com uops(NULL) 1137291Sgblack@eecs.umich.edu {} 1147291Sgblack@eecs.umich.edu 1157646Sgene.wu@arm.com virtual 1167646Sgene.wu@arm.com ~RfeOp() 1177646Sgene.wu@arm.com { 1187747SAli.Saidi@ARM.com delete [] uops; 1197646Sgene.wu@arm.com } 1207646Sgene.wu@arm.com 1217646Sgene.wu@arm.com StaticInstPtr 12212616Sgabeblack@google.com fetchMicroop(MicroPC microPC) const override 1237646Sgene.wu@arm.com { 1247646Sgene.wu@arm.com assert(uops != NULL && microPC < numMicroops); 1257646Sgene.wu@arm.com return uops[microPC]; 1267646Sgene.wu@arm.com } 1277646Sgene.wu@arm.com 12812616Sgabeblack@google.com std::string generateDisassembly( 12912616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 1307291Sgblack@eecs.umich.edu}; 1317291Sgblack@eecs.umich.edu 1327312Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 1337720Sgblack@eecs.umich.educlass SrsOp : public MightBeMicro 1347312Sgblack@eecs.umich.edu{ 1357312Sgblack@eecs.umich.edu public: 1367312Sgblack@eecs.umich.edu enum AddrMode { 1377312Sgblack@eecs.umich.edu DecrementAfter, 1387312Sgblack@eecs.umich.edu DecrementBefore, 1397312Sgblack@eecs.umich.edu IncrementAfter, 1407312Sgblack@eecs.umich.edu IncrementBefore 1417312Sgblack@eecs.umich.edu }; 1427312Sgblack@eecs.umich.edu protected: 1437312Sgblack@eecs.umich.edu uint32_t regMode; 1447312Sgblack@eecs.umich.edu AddrMode mode; 1457312Sgblack@eecs.umich.edu bool wb; 1467646Sgene.wu@arm.com static const unsigned numMicroops = 2; 1477646Sgene.wu@arm.com 1487646Sgene.wu@arm.com StaticInstPtr *uops; 1497312Sgblack@eecs.umich.edu 1507312Sgblack@eecs.umich.edu SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1517312Sgblack@eecs.umich.edu uint32_t _regMode, AddrMode _mode, bool _wb) 1527720Sgblack@eecs.umich.edu : MightBeMicro(mnem, _machInst, __opClass), 1537646Sgene.wu@arm.com regMode(_regMode), mode(_mode), wb(_wb), uops(NULL) 1547312Sgblack@eecs.umich.edu {} 1557312Sgblack@eecs.umich.edu 1567646Sgene.wu@arm.com virtual 1577646Sgene.wu@arm.com ~SrsOp() 1587646Sgene.wu@arm.com { 1597845SAli.Saidi@ARM.com delete [] uops; 1607646Sgene.wu@arm.com } 1617646Sgene.wu@arm.com 1627646Sgene.wu@arm.com StaticInstPtr 16312616Sgabeblack@google.com fetchMicroop(MicroPC microPC) const override 1647646Sgene.wu@arm.com { 1657646Sgene.wu@arm.com assert(uops != NULL && microPC < numMicroops); 1667646Sgene.wu@arm.com return uops[microPC]; 1677646Sgene.wu@arm.com } 1687646Sgene.wu@arm.com 16912616Sgabeblack@google.com std::string generateDisassembly( 17012616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 1717312Sgblack@eecs.umich.edu}; 1727312Sgblack@eecs.umich.edu 1737720Sgblack@eecs.umich.educlass Memory : public MightBeMicro 1747118Sgblack@eecs.umich.edu{ 1757118Sgblack@eecs.umich.edu public: 1767118Sgblack@eecs.umich.edu enum AddrMode { 1777118Sgblack@eecs.umich.edu AddrMd_Offset, 1787118Sgblack@eecs.umich.edu AddrMd_PreIndex, 1797118Sgblack@eecs.umich.edu AddrMd_PostIndex 1807118Sgblack@eecs.umich.edu }; 1817118Sgblack@eecs.umich.edu 1827118Sgblack@eecs.umich.edu protected: 1837118Sgblack@eecs.umich.edu 1847118Sgblack@eecs.umich.edu IntRegIndex dest; 1857118Sgblack@eecs.umich.edu IntRegIndex base; 1867118Sgblack@eecs.umich.edu bool add; 1877646Sgene.wu@arm.com static const unsigned numMicroops = 3; 1887646Sgene.wu@arm.com 1897646Sgene.wu@arm.com StaticInstPtr *uops; 1907118Sgblack@eecs.umich.edu 1917132Sgblack@eecs.umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1927132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add) 1937720Sgblack@eecs.umich.edu : MightBeMicro(mnem, _machInst, __opClass), 1947646Sgene.wu@arm.com dest(_dest), base(_base), add(_add), uops(NULL) 1957118Sgblack@eecs.umich.edu {} 1967118Sgblack@eecs.umich.edu 1977646Sgene.wu@arm.com virtual 1987646Sgene.wu@arm.com ~Memory() 1997646Sgene.wu@arm.com { 2007646Sgene.wu@arm.com delete [] uops; 2017646Sgene.wu@arm.com } 2027646Sgene.wu@arm.com 2037646Sgene.wu@arm.com StaticInstPtr 20412616Sgabeblack@google.com fetchMicroop(MicroPC microPC) const override 2057646Sgene.wu@arm.com { 2067646Sgene.wu@arm.com assert(uops != NULL && microPC < numMicroops); 2077646Sgene.wu@arm.com return uops[microPC]; 2087646Sgene.wu@arm.com } 2097646Sgene.wu@arm.com 2107118Sgblack@eecs.umich.edu virtual void 2117118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 2127118Sgblack@eecs.umich.edu {} 2137118Sgblack@eecs.umich.edu 2147279Sgblack@eecs.umich.edu virtual void 2157279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2167279Sgblack@eecs.umich.edu { 21712104Snathanael.premillieu@arm.com printIntReg(os, dest); 2187279Sgblack@eecs.umich.edu } 2197279Sgblack@eecs.umich.edu 2207118Sgblack@eecs.umich.edu void printInst(std::ostream &os, AddrMode addrMode) const; 2217118Sgblack@eecs.umich.edu}; 2227118Sgblack@eecs.umich.edu 2237118Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 2247132Sgblack@eecs.umich.educlass MemoryImm : public Memory 2257118Sgblack@eecs.umich.edu{ 2267118Sgblack@eecs.umich.edu protected: 2277118Sgblack@eecs.umich.edu int32_t imm; 2287118Sgblack@eecs.umich.edu 2297132Sgblack@eecs.umich.edu MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2307132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) 2317132Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) 2327118Sgblack@eecs.umich.edu {} 2337118Sgblack@eecs.umich.edu 2347118Sgblack@eecs.umich.edu void 2357118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 2367118Sgblack@eecs.umich.edu { 2377118Sgblack@eecs.umich.edu int32_t pImm = imm; 2387118Sgblack@eecs.umich.edu if (!add) 2397118Sgblack@eecs.umich.edu pImm = -pImm; 2407118Sgblack@eecs.umich.edu ccprintf(os, "#%d", pImm); 2417118Sgblack@eecs.umich.edu } 2427118Sgblack@eecs.umich.edu}; 2437118Sgblack@eecs.umich.edu 2447303Sgblack@eecs.umich.educlass MemoryExImm : public MemoryImm 2457303Sgblack@eecs.umich.edu{ 2467303Sgblack@eecs.umich.edu protected: 2477303Sgblack@eecs.umich.edu IntRegIndex result; 2487303Sgblack@eecs.umich.edu 2497303Sgblack@eecs.umich.edu MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2507303Sgblack@eecs.umich.edu IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base, 2517303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 2527303Sgblack@eecs.umich.edu : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 2537303Sgblack@eecs.umich.edu result(_result) 2547303Sgblack@eecs.umich.edu {} 2557303Sgblack@eecs.umich.edu 2567303Sgblack@eecs.umich.edu void 2577303Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2587303Sgblack@eecs.umich.edu { 25912104Snathanael.premillieu@arm.com printIntReg(os, result); 2607303Sgblack@eecs.umich.edu os << ", "; 2617303Sgblack@eecs.umich.edu MemoryImm::printDest(os); 2627303Sgblack@eecs.umich.edu } 2637303Sgblack@eecs.umich.edu}; 2647303Sgblack@eecs.umich.edu 2657279Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 2667279Sgblack@eecs.umich.educlass MemoryDImm : public MemoryImm 2677279Sgblack@eecs.umich.edu{ 2687279Sgblack@eecs.umich.edu protected: 2697279Sgblack@eecs.umich.edu IntRegIndex dest2; 2707279Sgblack@eecs.umich.edu 2717279Sgblack@eecs.umich.edu MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2727279Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 2737279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 2747279Sgblack@eecs.umich.edu : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 2757279Sgblack@eecs.umich.edu dest2(_dest2) 2767279Sgblack@eecs.umich.edu {} 2777279Sgblack@eecs.umich.edu 2787279Sgblack@eecs.umich.edu void 2797279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2807279Sgblack@eecs.umich.edu { 2817279Sgblack@eecs.umich.edu MemoryImm::printDest(os); 2827279Sgblack@eecs.umich.edu os << ", "; 28312104Snathanael.premillieu@arm.com printIntReg(os, dest2); 2847279Sgblack@eecs.umich.edu } 2857279Sgblack@eecs.umich.edu}; 2867279Sgblack@eecs.umich.edu 2877303Sgblack@eecs.umich.educlass MemoryExDImm : public MemoryDImm 2887303Sgblack@eecs.umich.edu{ 2897303Sgblack@eecs.umich.edu protected: 2907303Sgblack@eecs.umich.edu IntRegIndex result; 2917303Sgblack@eecs.umich.edu 2927303Sgblack@eecs.umich.edu MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2937303Sgblack@eecs.umich.edu IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, 2947303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 2957303Sgblack@eecs.umich.edu : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2, 2967303Sgblack@eecs.umich.edu _base, _add, _imm), result(_result) 2977303Sgblack@eecs.umich.edu {} 2987303Sgblack@eecs.umich.edu 2997303Sgblack@eecs.umich.edu void 3007303Sgblack@eecs.umich.edu printDest(std::ostream &os) const 3017303Sgblack@eecs.umich.edu { 30212104Snathanael.premillieu@arm.com printIntReg(os, result); 3037303Sgblack@eecs.umich.edu os << ", "; 3047303Sgblack@eecs.umich.edu MemoryDImm::printDest(os); 3057303Sgblack@eecs.umich.edu } 3067303Sgblack@eecs.umich.edu}; 3077303Sgblack@eecs.umich.edu 3087118Sgblack@eecs.umich.edu// The address is a shifted register plus an immediate 3097132Sgblack@eecs.umich.educlass MemoryReg : public Memory 3107118Sgblack@eecs.umich.edu{ 3117118Sgblack@eecs.umich.edu protected: 3127118Sgblack@eecs.umich.edu int32_t shiftAmt; 3137118Sgblack@eecs.umich.edu ArmShiftType shiftType; 3147118Sgblack@eecs.umich.edu IntRegIndex index; 3157118Sgblack@eecs.umich.edu 3167132Sgblack@eecs.umich.edu MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 3177132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, 3187132Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3197132Sgblack@eecs.umich.edu IntRegIndex _index) 3207132Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _dest, _base, _add), 3217118Sgblack@eecs.umich.edu shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) 3227118Sgblack@eecs.umich.edu {} 3237118Sgblack@eecs.umich.edu 3247428Sgblack@eecs.umich.edu void printOffset(std::ostream &os) const; 3257118Sgblack@eecs.umich.edu}; 3267118Sgblack@eecs.umich.edu 3277279Sgblack@eecs.umich.educlass MemoryDReg : public MemoryReg 3287279Sgblack@eecs.umich.edu{ 3297279Sgblack@eecs.umich.edu protected: 3307279Sgblack@eecs.umich.edu IntRegIndex dest2; 3317279Sgblack@eecs.umich.edu 3327279Sgblack@eecs.umich.edu MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 3337279Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 3347279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3357279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3367279Sgblack@eecs.umich.edu IntRegIndex _index) 3377279Sgblack@eecs.umich.edu : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add, 3387279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index), 3397279Sgblack@eecs.umich.edu dest2(_dest2) 3407279Sgblack@eecs.umich.edu {} 3417279Sgblack@eecs.umich.edu 3427279Sgblack@eecs.umich.edu void 3437279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 3447279Sgblack@eecs.umich.edu { 3457279Sgblack@eecs.umich.edu MemoryReg::printDest(os); 3467279Sgblack@eecs.umich.edu os << ", "; 34712104Snathanael.premillieu@arm.com printIntReg(os, dest2); 3487279Sgblack@eecs.umich.edu } 3497279Sgblack@eecs.umich.edu}; 3507279Sgblack@eecs.umich.edu 3517118Sgblack@eecs.umich.edutemplate<class Base> 3527132Sgblack@eecs.umich.educlass MemoryOffset : public Base 3537118Sgblack@eecs.umich.edu{ 3547118Sgblack@eecs.umich.edu protected: 3557132Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3567132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3577132Sgblack@eecs.umich.edu bool _add, int32_t _imm) 3587132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3597132Sgblack@eecs.umich.edu {} 3607132Sgblack@eecs.umich.edu 3617132Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3627132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3637132Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3647132Sgblack@eecs.umich.edu IntRegIndex _index) 3657132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3667132Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3677132Sgblack@eecs.umich.edu {} 3687132Sgblack@eecs.umich.edu 3697279Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3707279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3717279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3727279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3737279Sgblack@eecs.umich.edu {} 3747279Sgblack@eecs.umich.edu 3757279Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3767303Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 3777303Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 3787303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3797303Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 3807303Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 3817303Sgblack@eecs.umich.edu {} 3827303Sgblack@eecs.umich.edu 3837303Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3847279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3857279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3867279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3877279Sgblack@eecs.umich.edu IntRegIndex _index) 3887279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3897279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3907279Sgblack@eecs.umich.edu {} 3917279Sgblack@eecs.umich.edu 3927132Sgblack@eecs.umich.edu std::string 3937132Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 3947132Sgblack@eecs.umich.edu { 3957132Sgblack@eecs.umich.edu std::stringstream ss; 3967132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_Offset); 3977132Sgblack@eecs.umich.edu return ss.str(); 3987132Sgblack@eecs.umich.edu } 3997132Sgblack@eecs.umich.edu}; 4007132Sgblack@eecs.umich.edu 4017132Sgblack@eecs.umich.edutemplate<class Base> 4027132Sgblack@eecs.umich.educlass MemoryPreIndex : public Base 4037132Sgblack@eecs.umich.edu{ 4047132Sgblack@eecs.umich.edu protected: 4057132Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4067132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4077132Sgblack@eecs.umich.edu bool _add, int32_t _imm) 4087132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 4097132Sgblack@eecs.umich.edu {} 4107132Sgblack@eecs.umich.edu 4117132Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4127132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4137132Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 4147132Sgblack@eecs.umich.edu IntRegIndex _index) 4157132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 4167132Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4177132Sgblack@eecs.umich.edu {} 4187132Sgblack@eecs.umich.edu 4197279Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4207279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4217279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4227279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 4237279Sgblack@eecs.umich.edu {} 4247279Sgblack@eecs.umich.edu 4257279Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4267303Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 4277303Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 4287303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4297303Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 4307303Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 4317303Sgblack@eecs.umich.edu {} 4327303Sgblack@eecs.umich.edu 4337303Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4347279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4357279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 4367279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 4377279Sgblack@eecs.umich.edu IntRegIndex _index) 4387279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 4397279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4407279Sgblack@eecs.umich.edu {} 4417279Sgblack@eecs.umich.edu 4427132Sgblack@eecs.umich.edu std::string 4437132Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 4447132Sgblack@eecs.umich.edu { 4457132Sgblack@eecs.umich.edu std::stringstream ss; 4467132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PreIndex); 4477132Sgblack@eecs.umich.edu return ss.str(); 4487132Sgblack@eecs.umich.edu } 4497132Sgblack@eecs.umich.edu}; 4507132Sgblack@eecs.umich.edu 4517132Sgblack@eecs.umich.edutemplate<class Base> 4527132Sgblack@eecs.umich.educlass MemoryPostIndex : public Base 4537132Sgblack@eecs.umich.edu{ 4547132Sgblack@eecs.umich.edu protected: 4557132Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4567118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4577118Sgblack@eecs.umich.edu bool _add, int32_t _imm) 4587118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 4597118Sgblack@eecs.umich.edu {} 4607118Sgblack@eecs.umich.edu 4617132Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4627118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4637118Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 4647118Sgblack@eecs.umich.edu IntRegIndex _index) 4657118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 4667118Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4677118Sgblack@eecs.umich.edu {} 4687118Sgblack@eecs.umich.edu 4697279Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4707279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4717279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4727279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 4737279Sgblack@eecs.umich.edu {} 4747279Sgblack@eecs.umich.edu 4757279Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4767303Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 4777303Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 4787303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4797303Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 4807303Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 4817303Sgblack@eecs.umich.edu {} 4827303Sgblack@eecs.umich.edu 4837303Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4847279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4857279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 4867279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 4877279Sgblack@eecs.umich.edu IntRegIndex _index) 4887279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 4897279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4907279Sgblack@eecs.umich.edu {} 4917279Sgblack@eecs.umich.edu 4927118Sgblack@eecs.umich.edu std::string 4937118Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 4947118Sgblack@eecs.umich.edu { 4957118Sgblack@eecs.umich.edu std::stringstream ss; 4967132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PostIndex); 4977118Sgblack@eecs.umich.edu return ss.str(); 4987118Sgblack@eecs.umich.edu } 4997118Sgblack@eecs.umich.edu}; 5006253Sgblack@eecs.umich.edu} 5016253Sgblack@eecs.umich.edu 5026253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MEM_HH__ 503