mem.cc revision 7312
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#include "arch/arm/insts/mem.hh" 44#include "base/loader/symtab.hh" 45 46using namespace std; 47 48namespace ArmISA 49{ 50 51string 52Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const 53{ 54 stringstream ss; 55 printMnemonic(ss); 56 printReg(ss, dest); 57 ss << ", "; 58 printReg(ss, op1); 59 ss << ", ["; 60 printReg(ss, base); 61 ss << "]"; 62 return ss.str(); 63} 64 65string 66RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 67{ 68 stringstream ss; 69 switch (mode) { 70 case DecrementAfter: 71 printMnemonic(ss, "da"); 72 break; 73 case DecrementBefore: 74 printMnemonic(ss, "db"); 75 break; 76 case IncrementAfter: 77 printMnemonic(ss, "ia"); 78 break; 79 case IncrementBefore: 80 printMnemonic(ss, "ib"); 81 break; 82 } 83 printReg(ss, base); 84 if (wb) { 85 ss << "!"; 86 } 87 return ss.str(); 88} 89 90string 91SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 92{ 93 stringstream ss; 94 switch (mode) { 95 case DecrementAfter: 96 printMnemonic(ss, "da"); 97 break; 98 case DecrementBefore: 99 printMnemonic(ss, "db"); 100 break; 101 case IncrementAfter: 102 printMnemonic(ss, "ia"); 103 break; 104 case IncrementBefore: 105 printMnemonic(ss, "ib"); 106 break; 107 } 108 printReg(ss, INTREG_SP); 109 if (wb) { 110 ss << "!"; 111 } 112 ss << ", #"; 113 switch (mode) { 114 case MODE_USER: 115 ss << "user"; 116 break; 117 case MODE_FIQ: 118 ss << "fiq"; 119 break; 120 case MODE_IRQ: 121 ss << "irq"; 122 break; 123 case MODE_SVC: 124 ss << "supervisor"; 125 break; 126 case MODE_MON: 127 ss << "monitor"; 128 break; 129 case MODE_ABORT: 130 ss << "abort"; 131 break; 132 case MODE_UNDEFINED: 133 ss << "undefined"; 134 break; 135 case MODE_SYSTEM: 136 ss << "system"; 137 break; 138 default: 139 ss << "unrecognized"; 140 break; 141 } 142 return ss.str(); 143} 144 145void 146Memory::printInst(std::ostream &os, AddrMode addrMode) const 147{ 148 printMnemonic(os); 149 printDest(os); 150 os << ", ["; 151 printReg(os, base); 152 if (addrMode != AddrMd_PostIndex) { 153 os << ", "; 154 printOffset(os); 155 os << "]"; 156 if (addrMode == AddrMd_PreIndex) { 157 os << "!"; 158 } 159 } else { 160 os << "] "; 161 printOffset(os); 162 163 } 164} 165 166} 167