mem.cc revision 7291:2d21be52e57f 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/mem.hh"
44#include "base/loader/symtab.hh"
45
46using namespace std;
47
48namespace ArmISA
49{
50
51string
52Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
53{
54    stringstream ss;
55    printMnemonic(ss);
56    printReg(ss, dest);
57    ss << ", ";
58    printReg(ss, op1);
59    ss << ", [";
60    printReg(ss, base);
61    ss << "]";
62    return ss.str();
63}
64
65string
66RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
67{
68    stringstream ss;
69    switch (mode) {
70      case DecrementAfter:
71        printMnemonic(ss, "da");
72        break;
73      case DecrementBefore:
74        printMnemonic(ss, "db");
75        break;
76      case IncrementAfter:
77        printMnemonic(ss, "ia");
78        break;
79      case IncrementBefore:
80        printMnemonic(ss, "ib");
81        break;
82    }
83    printReg(ss, base);
84    if (wb) {
85        ss << "!";
86    }
87    return ss.str();
88}
89
90void
91Memory::printInst(std::ostream &os, AddrMode addrMode) const
92{
93    printMnemonic(os);
94    printDest(os);
95    os << ", [";
96    printReg(os, base);
97    if (addrMode != AddrMd_PostIndex) {
98        os << ", ";
99        printOffset(os);
100        os << "]";
101        if (addrMode == AddrMd_PreIndex) {
102            os << "!";
103        }
104    } else {
105        os << "] ";
106        printOffset(os);
107
108    }
109}
110
111}
112