macromem.hh revision 8140:7449084b1612 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MACROMEM_HH__
43#define __ARCH_ARM_MACROMEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46#include "arch/arm/tlb.hh"
47
48namespace ArmISA
49{
50
51static inline unsigned int
52number_of_ones(int32_t val)
53{
54    uint32_t ones = 0;
55    for (int i = 0; i < 32; i++ )
56    {
57        if ( val & (1<<i) )
58            ones++;
59    }
60    return ones;
61}
62
63/**
64 * Base class for Memory microops
65 */
66class MicroOp : public PredOp
67{
68  protected:
69    MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
70            : PredOp(mnem, machInst, __opClass)
71    {
72    }
73
74  public:
75    void
76    advancePC(PCState &pcState) const
77    {
78        if (flags[IsLastMicroop]) {
79            pcState.uEnd();
80        } else if (flags[IsMicroop]) {
81            pcState.uAdvance();
82        } else {
83            pcState.advance();
84        }
85    }
86};
87
88/**
89 * Microops for Neon loads/stores
90 */
91class MicroNeonMemOp : public MicroOp
92{
93  protected:
94    RegIndex dest, ura;
95    uint32_t imm;
96    unsigned memAccessFlags;
97
98    MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
99                   RegIndex _dest, RegIndex _ura, uint32_t _imm)
100            : MicroOp(mnem, machInst, __opClass),
101              dest(_dest), ura(_ura), imm(_imm),
102              memAccessFlags(TLB::MustBeOne)
103    {
104    }
105};
106
107/**
108 * Microops for Neon load/store (de)interleaving
109 */
110class MicroNeonMixOp : public MicroOp
111{
112  protected:
113    RegIndex dest, op1;
114    uint32_t step;
115
116    MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
117                   RegIndex _dest, RegIndex _op1, uint32_t _step)
118            : MicroOp(mnem, machInst, __opClass),
119              dest(_dest), op1(_op1), step(_step)
120    {
121    }
122};
123
124class MicroNeonMixLaneOp : public MicroNeonMixOp
125{
126  protected:
127    unsigned lane;
128
129    MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
130                       OpClass __opClass, RegIndex _dest, RegIndex _op1,
131                       uint32_t _step, unsigned _lane)
132            : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
133              lane(_lane)
134    {
135    }
136};
137
138/**
139 * Microops of the form
140 * PC   = IntRegA
141 * CPSR = IntRegB
142 */
143class MicroSetPCCPSR : public MicroOp
144{
145    protected:
146    IntRegIndex ura, urb, urc;
147
148    MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
149                   IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
150        : MicroOp(mnem, machInst, __opClass),
151          ura(_ura), urb(_urb), urc(_urc)
152    {
153    }
154
155    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
156};
157
158/**
159 * Microops of the form IntRegA = IntRegB
160 */
161class MicroIntMov : public MicroOp
162{
163  protected:
164    RegIndex ura, urb;
165
166    MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
167               RegIndex _ura, RegIndex _urb)
168            : MicroOp(mnem, machInst, __opClass),
169              ura(_ura), urb(_urb)
170    {
171    }
172
173    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
174};
175
176/**
177 * Microops of the form IntRegA = IntRegB op Imm
178 */
179class MicroIntImmOp : public MicroOp
180{
181  protected:
182    RegIndex ura, urb;
183    uint32_t imm;
184
185    MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
186                  RegIndex _ura, RegIndex _urb, uint32_t _imm)
187            : MicroOp(mnem, machInst, __opClass),
188              ura(_ura), urb(_urb), imm(_imm)
189    {
190    }
191
192    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
193};
194
195/**
196 * Microops of the form IntRegA = IntRegB op IntRegC
197 */
198class MicroIntOp : public MicroOp
199{
200  protected:
201    RegIndex ura, urb, urc;
202
203    MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
204               RegIndex _ura, RegIndex _urb, RegIndex _urc)
205            : MicroOp(mnem, machInst, __opClass),
206              ura(_ura), urb(_urb), urc(_urc)
207    {
208    }
209
210    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
211};
212
213/**
214 * Microops of the form IntRegA = IntRegB op shifted IntRegC
215 */
216class MicroIntRegOp : public MicroOp
217{
218  protected:
219    RegIndex ura, urb, urc;
220    int32_t shiftAmt;
221    ArmShiftType shiftType;
222
223    MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
224               RegIndex _ura, RegIndex _urb, RegIndex _urc,
225               int32_t _shiftAmt, ArmShiftType _shiftType)
226            : MicroOp(mnem, machInst, __opClass),
227              ura(_ura), urb(_urb), urc(_urc),
228              shiftAmt(_shiftAmt), shiftType(_shiftType)
229    {
230    }
231};
232
233/**
234 * Memory microops which use IntReg + Imm addressing
235 */
236class MicroMemOp : public MicroIntImmOp
237{
238  protected:
239    bool up;
240    unsigned memAccessFlags;
241
242    MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
243               RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
244            : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
245              up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
246    {
247    }
248
249    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
250};
251
252/**
253 * Base class for microcoded integer memory instructions.
254 */
255class MacroMemOp : public PredMacroOp
256{
257  protected:
258    MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
259               IntRegIndex rn, bool index, bool up, bool user,
260               bool writeback, bool load, uint32_t reglist);
261};
262
263/**
264 * Base classes for microcoded integer memory instructions.
265 */
266class VldMultOp : public PredMacroOp
267{
268  protected:
269    VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
270              unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
271              unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
272};
273
274class VldSingleOp : public PredMacroOp
275{
276  protected:
277    VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
278                bool all, unsigned elems, RegIndex rn, RegIndex vd,
279                unsigned regs, unsigned inc, uint32_t size,
280                uint32_t align, RegIndex rm, unsigned lane);
281};
282
283/**
284 * Base class for microcoded integer memory instructions.
285 */
286class VstMultOp : public PredMacroOp
287{
288  protected:
289    VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
290              unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
291              unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
292};
293
294class VstSingleOp : public PredMacroOp
295{
296  protected:
297    VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
298                bool all, unsigned elems, RegIndex rn, RegIndex vd,
299                unsigned regs, unsigned inc, uint32_t size,
300                uint32_t align, RegIndex rm, unsigned lane);
301};
302
303/**
304 * Base class for microcoded floating point memory instructions.
305 */
306class MacroVFPMemOp : public PredMacroOp
307{
308  protected:
309    MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
310                  IntRegIndex rn, RegIndex vd, bool single, bool up,
311                  bool writeback, bool load, uint32_t offset);
312};
313
314}
315
316#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
317