macromem.hh revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MACROMEM_HH__
43#define __ARCH_ARM_MACROMEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46#include "arch/arm/tlb.hh"
47
48namespace ArmISA
49{
50
51static inline unsigned int
52number_of_ones(int32_t val)
53{
54    uint32_t ones = 0;
55    for (int i = 0; i < 32; i++ )
56    {
57        if ( val & (1<<i) )
58            ones++;
59    }
60    return ones;
61}
62
63/**
64 * Base class for Memory microops
65 */
66class MicroOp : public PredOp
67{
68  protected:
69    MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
70            : PredOp(mnem, machInst, __opClass)
71    {
72    }
73
74  public:
75    void
76    setDelayedCommit()
77    {
78        flags[IsDelayedCommit] = true;
79    }
80
81    void
82    advancePC(PCState &pcState) const
83    {
84        if (flags[IsLastMicroop]) {
85            pcState.uEnd();
86        } else if (flags[IsMicroop]) {
87            pcState.uAdvance();
88        } else {
89            pcState.advance();
90        }
91    }
92};
93
94/**
95 * Microops for Neon loads/stores
96 */
97class MicroNeonMemOp : public MicroOp
98{
99  protected:
100    RegIndex dest, ura;
101    uint32_t imm;
102    unsigned memAccessFlags;
103
104    MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
105                   RegIndex _dest, RegIndex _ura, uint32_t _imm)
106            : MicroOp(mnem, machInst, __opClass),
107              dest(_dest), ura(_ura), imm(_imm),
108              memAccessFlags(TLB::MustBeOne)
109    {
110    }
111};
112
113/**
114 * Microops for Neon load/store (de)interleaving
115 */
116class MicroNeonMixOp : public MicroOp
117{
118  protected:
119    RegIndex dest, op1;
120    uint32_t step;
121
122    MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
123                   RegIndex _dest, RegIndex _op1, uint32_t _step)
124            : MicroOp(mnem, machInst, __opClass),
125              dest(_dest), op1(_op1), step(_step)
126    {
127    }
128};
129
130class MicroNeonMixLaneOp : public MicroNeonMixOp
131{
132  protected:
133    unsigned lane;
134
135    MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
136                       OpClass __opClass, RegIndex _dest, RegIndex _op1,
137                       uint32_t _step, unsigned _lane)
138            : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
139              lane(_lane)
140    {
141    }
142};
143/**
144 * Microops of the form IntRegA = IntRegB
145 */
146class MicroIntMov : public MicroOp
147{
148  protected:
149    RegIndex ura, urb;
150
151    MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
152               RegIndex _ura, RegIndex _urb)
153            : MicroOp(mnem, machInst, __opClass),
154              ura(_ura), urb(_urb)
155    {
156    }
157
158    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
159};
160
161/**
162 * Microops of the form IntRegA = IntRegB op Imm
163 */
164class MicroIntImmOp : public MicroOp
165{
166  protected:
167    RegIndex ura, urb;
168    uint32_t imm;
169
170    MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
171                  RegIndex _ura, RegIndex _urb, uint32_t _imm)
172            : MicroOp(mnem, machInst, __opClass),
173              ura(_ura), urb(_urb), imm(_imm)
174    {
175    }
176
177    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
178};
179
180/**
181 * Microops of the form IntRegA = IntRegB op IntRegC
182 */
183class MicroIntOp : public MicroOp
184{
185  protected:
186    RegIndex ura, urb, urc;
187
188    MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
189               RegIndex _ura, RegIndex _urb, RegIndex _urc)
190            : MicroOp(mnem, machInst, __opClass),
191              ura(_ura), urb(_urb), urc(_urc)
192    {
193    }
194
195    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
196};
197
198/**
199 * Microops of the form IntRegA = IntRegB op shifted IntRegC
200 */
201class MicroIntRegOp : public MicroOp
202{
203  protected:
204    RegIndex ura, urb, urc;
205    int32_t shiftAmt;
206    ArmShiftType shiftType;
207
208    MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
209               RegIndex _ura, RegIndex _urb, RegIndex _urc,
210               int32_t _shiftAmt, ArmShiftType _shiftType)
211            : MicroOp(mnem, machInst, __opClass),
212              ura(_ura), urb(_urb), urc(_urc),
213              shiftAmt(_shiftAmt), shiftType(_shiftType)
214    {
215    }
216};
217
218/**
219 * Memory microops which use IntReg + Imm addressing
220 */
221class MicroMemOp : public MicroIntImmOp
222{
223  protected:
224    bool up;
225    unsigned memAccessFlags;
226
227    MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
228               RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
229            : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
230              up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
231    {
232    }
233
234    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
235};
236
237/**
238 * Base class for microcoded integer memory instructions.
239 */
240class MacroMemOp : public PredMacroOp
241{
242  protected:
243    MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
244               IntRegIndex rn, bool index, bool up, bool user,
245               bool writeback, bool load, uint32_t reglist);
246};
247
248/**
249 * Base classes for microcoded integer memory instructions.
250 */
251class VldMultOp : public PredMacroOp
252{
253  protected:
254    VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
255              unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
256              unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
257};
258
259class VldSingleOp : public PredMacroOp
260{
261  protected:
262    VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
263                bool all, unsigned elems, RegIndex rn, RegIndex vd,
264                unsigned regs, unsigned inc, uint32_t size,
265                uint32_t align, RegIndex rm, unsigned lane);
266};
267
268/**
269 * Base class for microcoded integer memory instructions.
270 */
271class VstMultOp : public PredMacroOp
272{
273  protected:
274    VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
275              unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
276              unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
277};
278
279class VstSingleOp : public PredMacroOp
280{
281  protected:
282    VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
283                bool all, unsigned elems, RegIndex rn, RegIndex vd,
284                unsigned regs, unsigned inc, uint32_t size,
285                uint32_t align, RegIndex rm, unsigned lane);
286};
287
288/**
289 * Base class for microcoded floating point memory instructions.
290 */
291class MacroVFPMemOp : public PredMacroOp
292{
293  protected:
294    MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
295                  IntRegIndex rn, RegIndex vd, bool single, bool up,
296                  bool writeback, bool load, uint32_t offset);
297};
298
299}
300
301#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
302