macromem.hh revision 7639
17130Sgblack@eecs.umich.edu/* 27130Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37130Sgblack@eecs.umich.edu * All rights reserved 47130Sgblack@eecs.umich.edu * 57130Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67130Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77130Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87130Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97130Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107130Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117130Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127130Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137130Sgblack@eecs.umich.edu * 147130Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MACROMEM_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_MACROMEM_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 467294Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 476253Sgblack@eecs.umich.edu 486253Sgblack@eecs.umich.edunamespace ArmISA 496253Sgblack@eecs.umich.edu{ 506253Sgblack@eecs.umich.edu 516253Sgblack@eecs.umich.edustatic inline unsigned int 526253Sgblack@eecs.umich.edunumber_of_ones(int32_t val) 536253Sgblack@eecs.umich.edu{ 546253Sgblack@eecs.umich.edu uint32_t ones = 0; 556253Sgblack@eecs.umich.edu for (int i = 0; i < 32; i++ ) 566253Sgblack@eecs.umich.edu { 576253Sgblack@eecs.umich.edu if ( val & (1<<i) ) 586253Sgblack@eecs.umich.edu ones++; 596253Sgblack@eecs.umich.edu } 606253Sgblack@eecs.umich.edu return ones; 616253Sgblack@eecs.umich.edu} 626253Sgblack@eecs.umich.edu 637431Sgblack@eecs.umich.edu/** 647431Sgblack@eecs.umich.edu * Base class for Memory microops 657431Sgblack@eecs.umich.edu */ 667343Sgblack@eecs.umich.educlass MicroOp : public PredOp 677343Sgblack@eecs.umich.edu{ 687343Sgblack@eecs.umich.edu protected: 697343Sgblack@eecs.umich.edu MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 707343Sgblack@eecs.umich.edu : PredOp(mnem, machInst, __opClass) 717343Sgblack@eecs.umich.edu { 727343Sgblack@eecs.umich.edu } 737343Sgblack@eecs.umich.edu 747343Sgblack@eecs.umich.edu public: 757343Sgblack@eecs.umich.edu void 767343Sgblack@eecs.umich.edu setDelayedCommit() 777343Sgblack@eecs.umich.edu { 787343Sgblack@eecs.umich.edu flags[IsDelayedCommit] = true; 797343Sgblack@eecs.umich.edu } 807343Sgblack@eecs.umich.edu}; 817343Sgblack@eecs.umich.edu 826253Sgblack@eecs.umich.edu/** 837639Sgblack@eecs.umich.edu * Microops for Neon loads/stores 847639Sgblack@eecs.umich.edu */ 857639Sgblack@eecs.umich.educlass MicroNeonMemOp : public MicroOp 867639Sgblack@eecs.umich.edu{ 877639Sgblack@eecs.umich.edu protected: 887639Sgblack@eecs.umich.edu RegIndex dest, ura; 897639Sgblack@eecs.umich.edu uint32_t imm; 907639Sgblack@eecs.umich.edu unsigned memAccessFlags; 917639Sgblack@eecs.umich.edu 927639Sgblack@eecs.umich.edu MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 937639Sgblack@eecs.umich.edu RegIndex _dest, RegIndex _ura, uint32_t _imm) 947639Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 957639Sgblack@eecs.umich.edu dest(_dest), ura(_ura), imm(_imm), 967639Sgblack@eecs.umich.edu memAccessFlags(TLB::MustBeOne) 977639Sgblack@eecs.umich.edu { 987639Sgblack@eecs.umich.edu } 997639Sgblack@eecs.umich.edu}; 1007639Sgblack@eecs.umich.edu 1017639Sgblack@eecs.umich.edu/** 1027639Sgblack@eecs.umich.edu * Microops for Neon load/store (de)interleaving 1037639Sgblack@eecs.umich.edu */ 1047639Sgblack@eecs.umich.educlass MicroNeonMixOp : public MicroOp 1057639Sgblack@eecs.umich.edu{ 1067639Sgblack@eecs.umich.edu protected: 1077639Sgblack@eecs.umich.edu RegIndex dest, op1; 1087639Sgblack@eecs.umich.edu uint32_t step; 1097639Sgblack@eecs.umich.edu 1107639Sgblack@eecs.umich.edu MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1117639Sgblack@eecs.umich.edu RegIndex _dest, RegIndex _op1, uint32_t _step) 1127639Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 1137639Sgblack@eecs.umich.edu dest(_dest), op1(_op1), step(_step) 1147639Sgblack@eecs.umich.edu { 1157639Sgblack@eecs.umich.edu } 1167639Sgblack@eecs.umich.edu}; 1177639Sgblack@eecs.umich.edu 1187639Sgblack@eecs.umich.educlass MicroNeonMixLaneOp : public MicroNeonMixOp 1197639Sgblack@eecs.umich.edu{ 1207639Sgblack@eecs.umich.edu protected: 1217639Sgblack@eecs.umich.edu unsigned lane; 1227639Sgblack@eecs.umich.edu 1237639Sgblack@eecs.umich.edu MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 1247639Sgblack@eecs.umich.edu OpClass __opClass, RegIndex _dest, RegIndex _op1, 1257639Sgblack@eecs.umich.edu uint32_t _step, unsigned _lane) 1267639Sgblack@eecs.umich.edu : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 1277639Sgblack@eecs.umich.edu lane(_lane) 1287639Sgblack@eecs.umich.edu { 1297639Sgblack@eecs.umich.edu } 1307639Sgblack@eecs.umich.edu}; 1317639Sgblack@eecs.umich.edu 1327639Sgblack@eecs.umich.edu/** 1336308Sgblack@eecs.umich.edu * Microops of the form IntRegA = IntRegB op Imm 1346308Sgblack@eecs.umich.edu */ 1357639Sgblack@eecs.umich.educlass MicroIntImmOp : public MicroOp 1366308Sgblack@eecs.umich.edu{ 1376308Sgblack@eecs.umich.edu protected: 1386308Sgblack@eecs.umich.edu RegIndex ura, urb; 1396308Sgblack@eecs.umich.edu uint8_t imm; 1406308Sgblack@eecs.umich.edu 1417639Sgblack@eecs.umich.edu MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1427639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, uint8_t _imm) 1437343Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 1446308Sgblack@eecs.umich.edu ura(_ura), urb(_urb), imm(_imm) 1456308Sgblack@eecs.umich.edu { 1466308Sgblack@eecs.umich.edu } 1477615Sminkyu.jeong@arm.com 1487615Sminkyu.jeong@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1496308Sgblack@eecs.umich.edu}; 1506308Sgblack@eecs.umich.edu 1516308Sgblack@eecs.umich.edu/** 1527639Sgblack@eecs.umich.edu * Microops of the form IntRegA = IntRegB op IntRegC 1537639Sgblack@eecs.umich.edu */ 1547639Sgblack@eecs.umich.educlass MicroIntOp : public MicroOp 1557639Sgblack@eecs.umich.edu{ 1567639Sgblack@eecs.umich.edu protected: 1577639Sgblack@eecs.umich.edu RegIndex ura, urb, urc; 1587639Sgblack@eecs.umich.edu 1597639Sgblack@eecs.umich.edu MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1607639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc) 1617639Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 1627639Sgblack@eecs.umich.edu ura(_ura), urb(_urb), urc(_urc) 1637639Sgblack@eecs.umich.edu { 1647639Sgblack@eecs.umich.edu } 1657639Sgblack@eecs.umich.edu 1667639Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1677639Sgblack@eecs.umich.edu}; 1687639Sgblack@eecs.umich.edu 1697639Sgblack@eecs.umich.edu/** 1706309Sgblack@eecs.umich.edu * Memory microops which use IntReg + Imm addressing 1716309Sgblack@eecs.umich.edu */ 1727639Sgblack@eecs.umich.educlass MicroMemOp : public MicroIntImmOp 1736309Sgblack@eecs.umich.edu{ 1746309Sgblack@eecs.umich.edu protected: 1757134Sgblack@eecs.umich.edu bool up; 1766309Sgblack@eecs.umich.edu unsigned memAccessFlags; 1776309Sgblack@eecs.umich.edu 1786309Sgblack@eecs.umich.edu MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1797134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 1807639Sgblack@eecs.umich.edu : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 1817294Sgblack@eecs.umich.edu up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 1826309Sgblack@eecs.umich.edu { 1836309Sgblack@eecs.umich.edu } 1847615Sminkyu.jeong@arm.com 1857615Sminkyu.jeong@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1866309Sgblack@eecs.umich.edu}; 1876309Sgblack@eecs.umich.edu 1887431Sgblack@eecs.umich.edu/** 1897431Sgblack@eecs.umich.edu * Base class for microcoded integer memory instructions. 1907431Sgblack@eecs.umich.edu */ 1917170Sgblack@eecs.umich.educlass MacroMemOp : public PredMacroOp 1927170Sgblack@eecs.umich.edu{ 1937170Sgblack@eecs.umich.edu protected: 1947170Sgblack@eecs.umich.edu MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1957170Sgblack@eecs.umich.edu IntRegIndex rn, bool index, bool up, bool user, 1967170Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t reglist); 1977170Sgblack@eecs.umich.edu}; 1987170Sgblack@eecs.umich.edu 1997431Sgblack@eecs.umich.edu/** 2007639Sgblack@eecs.umich.edu * Base classes for microcoded integer memory instructions. 2017639Sgblack@eecs.umich.edu */ 2027639Sgblack@eecs.umich.educlass VldMultOp : public PredMacroOp 2037639Sgblack@eecs.umich.edu{ 2047639Sgblack@eecs.umich.edu protected: 2057639Sgblack@eecs.umich.edu VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2067639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 2077639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 2087639Sgblack@eecs.umich.edu}; 2097639Sgblack@eecs.umich.edu 2107639Sgblack@eecs.umich.educlass VldSingleOp : public PredMacroOp 2117639Sgblack@eecs.umich.edu{ 2127639Sgblack@eecs.umich.edu protected: 2137639Sgblack@eecs.umich.edu VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2147639Sgblack@eecs.umich.edu bool all, unsigned elems, RegIndex rn, RegIndex vd, 2157639Sgblack@eecs.umich.edu unsigned regs, unsigned inc, uint32_t size, 2167639Sgblack@eecs.umich.edu uint32_t align, RegIndex rm, unsigned lane); 2177639Sgblack@eecs.umich.edu}; 2187639Sgblack@eecs.umich.edu 2197639Sgblack@eecs.umich.edu/** 2207639Sgblack@eecs.umich.edu * Base class for microcoded integer memory instructions. 2217639Sgblack@eecs.umich.edu */ 2227639Sgblack@eecs.umich.educlass VstMultOp : public PredMacroOp 2237639Sgblack@eecs.umich.edu{ 2247639Sgblack@eecs.umich.edu protected: 2257639Sgblack@eecs.umich.edu VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2267639Sgblack@eecs.umich.edu unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 2277639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 2287639Sgblack@eecs.umich.edu}; 2297639Sgblack@eecs.umich.edu 2307639Sgblack@eecs.umich.educlass VstSingleOp : public PredMacroOp 2317639Sgblack@eecs.umich.edu{ 2327639Sgblack@eecs.umich.edu protected: 2337639Sgblack@eecs.umich.edu VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2347639Sgblack@eecs.umich.edu bool all, unsigned elems, RegIndex rn, RegIndex vd, 2357639Sgblack@eecs.umich.edu unsigned regs, unsigned inc, uint32_t size, 2367639Sgblack@eecs.umich.edu uint32_t align, RegIndex rm, unsigned lane); 2377639Sgblack@eecs.umich.edu}; 2387639Sgblack@eecs.umich.edu 2397639Sgblack@eecs.umich.edu/** 2407431Sgblack@eecs.umich.edu * Base class for microcoded floating point memory instructions. 2417431Sgblack@eecs.umich.edu */ 2427175Sgblack@eecs.umich.educlass MacroVFPMemOp : public PredMacroOp 2437175Sgblack@eecs.umich.edu{ 2447175Sgblack@eecs.umich.edu protected: 2457175Sgblack@eecs.umich.edu MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2467175Sgblack@eecs.umich.edu IntRegIndex rn, RegIndex vd, bool single, bool up, 2477175Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t offset); 2487175Sgblack@eecs.umich.edu}; 2497175Sgblack@eecs.umich.edu 2506253Sgblack@eecs.umich.edu} 2516253Sgblack@eecs.umich.edu 2526253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ 253