macromem.hh revision 6726
16253Sgblack@eecs.umich.edu/* Copyright (c) 2007-2008 The Florida State University 26253Sgblack@eecs.umich.edu * All rights reserved. 36253Sgblack@eecs.umich.edu * 46253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 56253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 66253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 76253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 86253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 96253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 106253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 116253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 126253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 136253Sgblack@eecs.umich.edu * this software without specific prior written permission. 146253Sgblack@eecs.umich.edu * 156253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266253Sgblack@eecs.umich.edu * 276253Sgblack@eecs.umich.edu * Authors: Stephen Hines 286253Sgblack@eecs.umich.edu */ 296253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MACROMEM_HH__ 306253Sgblack@eecs.umich.edu#define __ARCH_ARM_MACROMEM_HH__ 316253Sgblack@eecs.umich.edu 326253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 336253Sgblack@eecs.umich.edu 346253Sgblack@eecs.umich.edunamespace ArmISA 356253Sgblack@eecs.umich.edu{ 366253Sgblack@eecs.umich.edu 376253Sgblack@eecs.umich.edustatic inline unsigned int 386253Sgblack@eecs.umich.edunumber_of_ones(int32_t val) 396253Sgblack@eecs.umich.edu{ 406253Sgblack@eecs.umich.edu uint32_t ones = 0; 416253Sgblack@eecs.umich.edu for (int i = 0; i < 32; i++ ) 426253Sgblack@eecs.umich.edu { 436253Sgblack@eecs.umich.edu if ( val & (1<<i) ) 446253Sgblack@eecs.umich.edu ones++; 456253Sgblack@eecs.umich.edu } 466253Sgblack@eecs.umich.edu return ones; 476253Sgblack@eecs.umich.edu} 486253Sgblack@eecs.umich.edu 496253Sgblack@eecs.umich.edu/** 506308Sgblack@eecs.umich.edu * Microops of the form IntRegA = IntRegB op Imm 516308Sgblack@eecs.umich.edu */ 526308Sgblack@eecs.umich.educlass MicroIntOp : public PredOp 536308Sgblack@eecs.umich.edu{ 546308Sgblack@eecs.umich.edu protected: 556308Sgblack@eecs.umich.edu RegIndex ura, urb; 566308Sgblack@eecs.umich.edu uint8_t imm; 576308Sgblack@eecs.umich.edu 586308Sgblack@eecs.umich.edu MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 596308Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, uint8_t _imm) 606308Sgblack@eecs.umich.edu : PredOp(mnem, machInst, __opClass), 616308Sgblack@eecs.umich.edu ura(_ura), urb(_urb), imm(_imm) 626308Sgblack@eecs.umich.edu { 636308Sgblack@eecs.umich.edu } 646308Sgblack@eecs.umich.edu}; 656308Sgblack@eecs.umich.edu 666308Sgblack@eecs.umich.edu/** 676309Sgblack@eecs.umich.edu * Memory microops which use IntReg + Imm addressing 686309Sgblack@eecs.umich.edu */ 696309Sgblack@eecs.umich.educlass MicroMemOp : public MicroIntOp 706309Sgblack@eecs.umich.edu{ 716309Sgblack@eecs.umich.edu protected: 726309Sgblack@eecs.umich.edu unsigned memAccessFlags; 736309Sgblack@eecs.umich.edu 746309Sgblack@eecs.umich.edu MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 756309Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, uint8_t _imm) 766309Sgblack@eecs.umich.edu : MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm), 776309Sgblack@eecs.umich.edu memAccessFlags(0) 786309Sgblack@eecs.umich.edu { 796309Sgblack@eecs.umich.edu } 806309Sgblack@eecs.umich.edu}; 816309Sgblack@eecs.umich.edu 826309Sgblack@eecs.umich.edu/** 836253Sgblack@eecs.umich.edu * Arm Macro Memory operations like LDM/STM 846253Sgblack@eecs.umich.edu */ 856253Sgblack@eecs.umich.educlass ArmMacroMemoryOp : public PredMacroOp 866253Sgblack@eecs.umich.edu{ 876726Sgblack@eecs.umich.edu protected: 886253Sgblack@eecs.umich.edu /// Memory request flags. See mem_req_base.hh. 896253Sgblack@eecs.umich.edu unsigned memAccessFlags; 906253Sgblack@eecs.umich.edu 916253Sgblack@eecs.umich.edu uint32_t reglist; 926253Sgblack@eecs.umich.edu uint32_t ones; 936253Sgblack@eecs.umich.edu 946253Sgblack@eecs.umich.edu ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst, 956305Sgblack@eecs.umich.edu OpClass __opClass) 966726Sgblack@eecs.umich.edu : PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0), 976726Sgblack@eecs.umich.edu reglist(machInst.regList), ones(0) 986253Sgblack@eecs.umich.edu { 996253Sgblack@eecs.umich.edu ones = number_of_ones(reglist); 1006726Sgblack@eecs.umich.edu numMicroops = ones + machInst.puswl.writeback + 1; 1016253Sgblack@eecs.umich.edu // Remember that writeback adds a uop 1026253Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1036253Sgblack@eecs.umich.edu } 1046253Sgblack@eecs.umich.edu}; 1056253Sgblack@eecs.umich.edu 1066253Sgblack@eecs.umich.edu/** 1076253Sgblack@eecs.umich.edu * Arm Macro FPA operations to fix ldfd and stfd instructions 1086253Sgblack@eecs.umich.edu */ 1096253Sgblack@eecs.umich.educlass ArmMacroFPAOp : public PredMacroOp 1106253Sgblack@eecs.umich.edu{ 1116726Sgblack@eecs.umich.edu protected: 1126253Sgblack@eecs.umich.edu uint32_t puswl, 1136253Sgblack@eecs.umich.edu prepost, 1146253Sgblack@eecs.umich.edu up, 1156253Sgblack@eecs.umich.edu psruser, 1166253Sgblack@eecs.umich.edu writeback, 1176253Sgblack@eecs.umich.edu loadop; 1186253Sgblack@eecs.umich.edu int32_t disp8; 1196253Sgblack@eecs.umich.edu 1206253Sgblack@eecs.umich.edu ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 1216253Sgblack@eecs.umich.edu : PredMacroOp(mnem, _machInst, __opClass), 1226253Sgblack@eecs.umich.edu puswl(machInst.puswl), 1236253Sgblack@eecs.umich.edu prepost(machInst.puswl.prepost), 1246253Sgblack@eecs.umich.edu up(machInst.puswl.up), 1256253Sgblack@eecs.umich.edu psruser(machInst.puswl.psruser), 1266253Sgblack@eecs.umich.edu writeback(machInst.puswl.writeback), 1276253Sgblack@eecs.umich.edu loadop(machInst.puswl.loadOp), 1286253Sgblack@eecs.umich.edu disp8(machInst.immed7_0 << 2) 1296253Sgblack@eecs.umich.edu { 1306253Sgblack@eecs.umich.edu numMicroops = 3 + writeback; 1316253Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1326253Sgblack@eecs.umich.edu } 1336253Sgblack@eecs.umich.edu}; 1346253Sgblack@eecs.umich.edu 1356253Sgblack@eecs.umich.edu/** 1366253Sgblack@eecs.umich.edu * Arm Macro FM operations to fix lfm and sfm 1376253Sgblack@eecs.umich.edu */ 1386253Sgblack@eecs.umich.educlass ArmMacroFMOp : public PredMacroOp 1396253Sgblack@eecs.umich.edu{ 1406726Sgblack@eecs.umich.edu protected: 1416253Sgblack@eecs.umich.edu uint32_t punwl, 1426253Sgblack@eecs.umich.edu prepost, 1436253Sgblack@eecs.umich.edu up, 1446253Sgblack@eecs.umich.edu n1bit, 1456253Sgblack@eecs.umich.edu writeback, 1466253Sgblack@eecs.umich.edu loadop, 1476253Sgblack@eecs.umich.edu n0bit, 1486253Sgblack@eecs.umich.edu count; 1496253Sgblack@eecs.umich.edu int32_t disp8; 1506253Sgblack@eecs.umich.edu 1516253Sgblack@eecs.umich.edu ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 1526253Sgblack@eecs.umich.edu : PredMacroOp(mnem, _machInst, __opClass), 1536253Sgblack@eecs.umich.edu punwl(machInst.punwl), 1546253Sgblack@eecs.umich.edu prepost(machInst.puswl.prepost), 1556253Sgblack@eecs.umich.edu up(machInst.puswl.up), 1566253Sgblack@eecs.umich.edu n1bit(machInst.opcode22), 1576253Sgblack@eecs.umich.edu writeback(machInst.puswl.writeback), 1586253Sgblack@eecs.umich.edu loadop(machInst.puswl.loadOp), 1596253Sgblack@eecs.umich.edu n0bit(machInst.opcode15), 1606253Sgblack@eecs.umich.edu disp8(machInst.immed7_0 << 2) 1616253Sgblack@eecs.umich.edu { 1626253Sgblack@eecs.umich.edu // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4) 1636253Sgblack@eecs.umich.edu count = (n1bit << 1) | n0bit; 1646253Sgblack@eecs.umich.edu if (count == 0) 1656253Sgblack@eecs.umich.edu count = 4; 1666253Sgblack@eecs.umich.edu numMicroops = (3*count) + writeback; 1676253Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1686253Sgblack@eecs.umich.edu } 1696253Sgblack@eecs.umich.edu}; 1706253Sgblack@eecs.umich.edu} 1716253Sgblack@eecs.umich.edu 1726253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ 173