macromem.hh revision 6308
16253Sgblack@eecs.umich.edu/* Copyright (c) 2007-2008 The Florida State University 26253Sgblack@eecs.umich.edu * All rights reserved. 36253Sgblack@eecs.umich.edu * 46253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 56253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 66253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 76253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 86253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 96253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 106253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 116253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 126253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 136253Sgblack@eecs.umich.edu * this software without specific prior written permission. 146253Sgblack@eecs.umich.edu * 156253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266253Sgblack@eecs.umich.edu * 276253Sgblack@eecs.umich.edu * Authors: Stephen Hines 286253Sgblack@eecs.umich.edu */ 296253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MACROMEM_HH__ 306253Sgblack@eecs.umich.edu#define __ARCH_ARM_MACROMEM_HH__ 316253Sgblack@eecs.umich.edu 326253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 336253Sgblack@eecs.umich.edu 346253Sgblack@eecs.umich.edunamespace ArmISA 356253Sgblack@eecs.umich.edu{ 366253Sgblack@eecs.umich.edu 376253Sgblack@eecs.umich.edustatic inline unsigned int 386253Sgblack@eecs.umich.edunumber_of_ones(int32_t val) 396253Sgblack@eecs.umich.edu{ 406253Sgblack@eecs.umich.edu uint32_t ones = 0; 416253Sgblack@eecs.umich.edu for (int i = 0; i < 32; i++ ) 426253Sgblack@eecs.umich.edu { 436253Sgblack@eecs.umich.edu if ( val & (1<<i) ) 446253Sgblack@eecs.umich.edu ones++; 456253Sgblack@eecs.umich.edu } 466253Sgblack@eecs.umich.edu return ones; 476253Sgblack@eecs.umich.edu} 486253Sgblack@eecs.umich.edu 496253Sgblack@eecs.umich.edu/** 506308Sgblack@eecs.umich.edu * Microops of the form IntRegA = IntRegB op Imm 516308Sgblack@eecs.umich.edu */ 526308Sgblack@eecs.umich.educlass MicroIntOp : public PredOp 536308Sgblack@eecs.umich.edu{ 546308Sgblack@eecs.umich.edu protected: 556308Sgblack@eecs.umich.edu RegIndex ura, urb; 566308Sgblack@eecs.umich.edu uint8_t imm; 576308Sgblack@eecs.umich.edu 586308Sgblack@eecs.umich.edu MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 596308Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, uint8_t _imm) 606308Sgblack@eecs.umich.edu : PredOp(mnem, machInst, __opClass), 616308Sgblack@eecs.umich.edu ura(_ura), urb(_urb), imm(_imm) 626308Sgblack@eecs.umich.edu { 636308Sgblack@eecs.umich.edu } 646308Sgblack@eecs.umich.edu}; 656308Sgblack@eecs.umich.edu 666308Sgblack@eecs.umich.edu/** 676253Sgblack@eecs.umich.edu * Arm Macro Memory operations like LDM/STM 686253Sgblack@eecs.umich.edu */ 696253Sgblack@eecs.umich.educlass ArmMacroMemoryOp : public PredMacroOp 706253Sgblack@eecs.umich.edu{ 716253Sgblack@eecs.umich.edu protected: 726253Sgblack@eecs.umich.edu /// Memory request flags. See mem_req_base.hh. 736253Sgblack@eecs.umich.edu unsigned memAccessFlags; 746253Sgblack@eecs.umich.edu 756253Sgblack@eecs.umich.edu uint32_t reglist; 766253Sgblack@eecs.umich.edu uint32_t ones; 776253Sgblack@eecs.umich.edu uint32_t puswl, 786253Sgblack@eecs.umich.edu prepost, 796253Sgblack@eecs.umich.edu up, 806253Sgblack@eecs.umich.edu psruser, 816253Sgblack@eecs.umich.edu writeback, 826253Sgblack@eecs.umich.edu loadop; 836253Sgblack@eecs.umich.edu 846253Sgblack@eecs.umich.edu ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst, 856305Sgblack@eecs.umich.edu OpClass __opClass) 866253Sgblack@eecs.umich.edu : PredMacroOp(mnem, _machInst, __opClass), 876253Sgblack@eecs.umich.edu memAccessFlags(0), 886253Sgblack@eecs.umich.edu reglist(machInst.regList), ones(0), 896253Sgblack@eecs.umich.edu puswl(machInst.puswl), 906253Sgblack@eecs.umich.edu prepost(machInst.puswl.prepost), 916253Sgblack@eecs.umich.edu up(machInst.puswl.up), 926253Sgblack@eecs.umich.edu psruser(machInst.puswl.psruser), 936253Sgblack@eecs.umich.edu writeback(machInst.puswl.writeback), 946253Sgblack@eecs.umich.edu loadop(machInst.puswl.loadOp) 956253Sgblack@eecs.umich.edu { 966253Sgblack@eecs.umich.edu ones = number_of_ones(reglist); 976253Sgblack@eecs.umich.edu numMicroops = ones + writeback + 1; 986253Sgblack@eecs.umich.edu // Remember that writeback adds a uop 996253Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1006253Sgblack@eecs.umich.edu } 1016253Sgblack@eecs.umich.edu}; 1026253Sgblack@eecs.umich.edu 1036253Sgblack@eecs.umich.edu/** 1046253Sgblack@eecs.umich.edu * Arm Macro FPA operations to fix ldfd and stfd instructions 1056253Sgblack@eecs.umich.edu */ 1066253Sgblack@eecs.umich.educlass ArmMacroFPAOp : public PredMacroOp 1076253Sgblack@eecs.umich.edu{ 1086253Sgblack@eecs.umich.edu protected: 1096253Sgblack@eecs.umich.edu uint32_t puswl, 1106253Sgblack@eecs.umich.edu prepost, 1116253Sgblack@eecs.umich.edu up, 1126253Sgblack@eecs.umich.edu psruser, 1136253Sgblack@eecs.umich.edu writeback, 1146253Sgblack@eecs.umich.edu loadop; 1156253Sgblack@eecs.umich.edu int32_t disp8; 1166253Sgblack@eecs.umich.edu 1176253Sgblack@eecs.umich.edu ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 1186253Sgblack@eecs.umich.edu : PredMacroOp(mnem, _machInst, __opClass), 1196253Sgblack@eecs.umich.edu puswl(machInst.puswl), 1206253Sgblack@eecs.umich.edu prepost(machInst.puswl.prepost), 1216253Sgblack@eecs.umich.edu up(machInst.puswl.up), 1226253Sgblack@eecs.umich.edu psruser(machInst.puswl.psruser), 1236253Sgblack@eecs.umich.edu writeback(machInst.puswl.writeback), 1246253Sgblack@eecs.umich.edu loadop(machInst.puswl.loadOp), 1256253Sgblack@eecs.umich.edu disp8(machInst.immed7_0 << 2) 1266253Sgblack@eecs.umich.edu { 1276253Sgblack@eecs.umich.edu numMicroops = 3 + writeback; 1286253Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1296253Sgblack@eecs.umich.edu } 1306253Sgblack@eecs.umich.edu}; 1316253Sgblack@eecs.umich.edu 1326253Sgblack@eecs.umich.edu/** 1336253Sgblack@eecs.umich.edu * Arm Macro FM operations to fix lfm and sfm 1346253Sgblack@eecs.umich.edu */ 1356253Sgblack@eecs.umich.educlass ArmMacroFMOp : public PredMacroOp 1366253Sgblack@eecs.umich.edu{ 1376253Sgblack@eecs.umich.edu protected: 1386253Sgblack@eecs.umich.edu uint32_t punwl, 1396253Sgblack@eecs.umich.edu prepost, 1406253Sgblack@eecs.umich.edu up, 1416253Sgblack@eecs.umich.edu n1bit, 1426253Sgblack@eecs.umich.edu writeback, 1436253Sgblack@eecs.umich.edu loadop, 1446253Sgblack@eecs.umich.edu n0bit, 1456253Sgblack@eecs.umich.edu count; 1466253Sgblack@eecs.umich.edu int32_t disp8; 1476253Sgblack@eecs.umich.edu 1486253Sgblack@eecs.umich.edu ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 1496253Sgblack@eecs.umich.edu : PredMacroOp(mnem, _machInst, __opClass), 1506253Sgblack@eecs.umich.edu punwl(machInst.punwl), 1516253Sgblack@eecs.umich.edu prepost(machInst.puswl.prepost), 1526253Sgblack@eecs.umich.edu up(machInst.puswl.up), 1536253Sgblack@eecs.umich.edu n1bit(machInst.opcode22), 1546253Sgblack@eecs.umich.edu writeback(machInst.puswl.writeback), 1556253Sgblack@eecs.umich.edu loadop(machInst.puswl.loadOp), 1566253Sgblack@eecs.umich.edu n0bit(machInst.opcode15), 1576253Sgblack@eecs.umich.edu disp8(machInst.immed7_0 << 2) 1586253Sgblack@eecs.umich.edu { 1596253Sgblack@eecs.umich.edu // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4) 1606253Sgblack@eecs.umich.edu count = (n1bit << 1) | n0bit; 1616253Sgblack@eecs.umich.edu if (count == 0) 1626253Sgblack@eecs.umich.edu count = 4; 1636253Sgblack@eecs.umich.edu numMicroops = (3*count) + writeback; 1646253Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1656253Sgblack@eecs.umich.edu } 1666253Sgblack@eecs.umich.edu}; 1676253Sgblack@eecs.umich.edu} 1686253Sgblack@eecs.umich.edu 1696253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ 170