macromem.hh revision 6305
1/* Copyright (c) 2007-2008 The Florida State University 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution; 11 * neither the name of the copyright holders nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Authors: Stephen Hines 28 */ 29#ifndef __ARCH_ARM_MACROMEM_HH__ 30#define __ARCH_ARM_MACROMEM_HH__ 31 32#include "arch/arm/insts/pred_inst.hh" 33 34namespace ArmISA 35{ 36 37static inline unsigned int 38number_of_ones(int32_t val) 39{ 40 uint32_t ones = 0; 41 for (int i = 0; i < 32; i++ ) 42 { 43 if ( val & (1<<i) ) 44 ones++; 45 } 46 return ones; 47} 48 49/** 50 * Arm Macro Memory operations like LDM/STM 51 */ 52class ArmMacroMemoryOp : public PredMacroOp 53{ 54 protected: 55 /// Memory request flags. See mem_req_base.hh. 56 unsigned memAccessFlags; 57 58 uint32_t reglist; 59 uint32_t ones; 60 uint32_t puswl, 61 prepost, 62 up, 63 psruser, 64 writeback, 65 loadop; 66 67 ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst, 68 OpClass __opClass) 69 : PredMacroOp(mnem, _machInst, __opClass), 70 memAccessFlags(0), 71 reglist(machInst.regList), ones(0), 72 puswl(machInst.puswl), 73 prepost(machInst.puswl.prepost), 74 up(machInst.puswl.up), 75 psruser(machInst.puswl.psruser), 76 writeback(machInst.puswl.writeback), 77 loadop(machInst.puswl.loadOp) 78 { 79 ones = number_of_ones(reglist); 80 numMicroops = ones + writeback + 1; 81 // Remember that writeback adds a uop 82 microOps = new StaticInstPtr[numMicroops]; 83 } 84}; 85 86/** 87 * Arm Macro FPA operations to fix ldfd and stfd instructions 88 */ 89class ArmMacroFPAOp : public PredMacroOp 90{ 91 protected: 92 uint32_t puswl, 93 prepost, 94 up, 95 psruser, 96 writeback, 97 loadop; 98 int32_t disp8; 99 100 ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 101 : PredMacroOp(mnem, _machInst, __opClass), 102 puswl(machInst.puswl), 103 prepost(machInst.puswl.prepost), 104 up(machInst.puswl.up), 105 psruser(machInst.puswl.psruser), 106 writeback(machInst.puswl.writeback), 107 loadop(machInst.puswl.loadOp), 108 disp8(machInst.immed7_0 << 2) 109 { 110 numMicroops = 3 + writeback; 111 microOps = new StaticInstPtr[numMicroops]; 112 } 113}; 114 115/** 116 * Arm Macro FM operations to fix lfm and sfm 117 */ 118class ArmMacroFMOp : public PredMacroOp 119{ 120 protected: 121 uint32_t punwl, 122 prepost, 123 up, 124 n1bit, 125 writeback, 126 loadop, 127 n0bit, 128 count; 129 int32_t disp8; 130 131 ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 132 : PredMacroOp(mnem, _machInst, __opClass), 133 punwl(machInst.punwl), 134 prepost(machInst.puswl.prepost), 135 up(machInst.puswl.up), 136 n1bit(machInst.opcode22), 137 writeback(machInst.puswl.writeback), 138 loadop(machInst.puswl.loadOp), 139 n0bit(machInst.opcode15), 140 disp8(machInst.immed7_0 << 2) 141 { 142 // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4) 143 count = (n1bit << 1) | n0bit; 144 if (count == 0) 145 count = 4; 146 numMicroops = (3*count) + writeback; 147 microOps = new StaticInstPtr[numMicroops]; 148 } 149}; 150} 151 152#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ 153