macromem.hh revision 10037
17130Sgblack@eecs.umich.edu/* 210037SARM gem5 Developers * Copyright (c) 2010-2013 ARM Limited 37130Sgblack@eecs.umich.edu * All rights reserved 47130Sgblack@eecs.umich.edu * 57130Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67130Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77130Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87130Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97130Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107130Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117130Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127130Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137130Sgblack@eecs.umich.edu * 147130Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MACROMEM_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_MACROMEM_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 467294Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 476253Sgblack@eecs.umich.edu 486253Sgblack@eecs.umich.edunamespace ArmISA 496253Sgblack@eecs.umich.edu{ 506253Sgblack@eecs.umich.edu 516253Sgblack@eecs.umich.edustatic inline unsigned int 526253Sgblack@eecs.umich.edunumber_of_ones(int32_t val) 536253Sgblack@eecs.umich.edu{ 546253Sgblack@eecs.umich.edu uint32_t ones = 0; 556253Sgblack@eecs.umich.edu for (int i = 0; i < 32; i++ ) 566253Sgblack@eecs.umich.edu { 576253Sgblack@eecs.umich.edu if ( val & (1<<i) ) 586253Sgblack@eecs.umich.edu ones++; 596253Sgblack@eecs.umich.edu } 606253Sgblack@eecs.umich.edu return ones; 616253Sgblack@eecs.umich.edu} 626253Sgblack@eecs.umich.edu 637431Sgblack@eecs.umich.edu/** 647431Sgblack@eecs.umich.edu * Base class for Memory microops 657431Sgblack@eecs.umich.edu */ 667343Sgblack@eecs.umich.educlass MicroOp : public PredOp 677343Sgblack@eecs.umich.edu{ 687343Sgblack@eecs.umich.edu protected: 697343Sgblack@eecs.umich.edu MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 707343Sgblack@eecs.umich.edu : PredOp(mnem, machInst, __opClass) 717343Sgblack@eecs.umich.edu { 727343Sgblack@eecs.umich.edu } 737343Sgblack@eecs.umich.edu 747343Sgblack@eecs.umich.edu public: 757343Sgblack@eecs.umich.edu void 767720Sgblack@eecs.umich.edu advancePC(PCState &pcState) const 777720Sgblack@eecs.umich.edu { 787720Sgblack@eecs.umich.edu if (flags[IsLastMicroop]) { 797720Sgblack@eecs.umich.edu pcState.uEnd(); 807720Sgblack@eecs.umich.edu } else if (flags[IsMicroop]) { 817720Sgblack@eecs.umich.edu pcState.uAdvance(); 827720Sgblack@eecs.umich.edu } else { 837720Sgblack@eecs.umich.edu pcState.advance(); 847720Sgblack@eecs.umich.edu } 857720Sgblack@eecs.umich.edu } 867343Sgblack@eecs.umich.edu}; 877343Sgblack@eecs.umich.edu 8810037SARM gem5 Developersclass MicroOpX : public ArmStaticInst 8910037SARM gem5 Developers{ 9010037SARM gem5 Developers protected: 9110037SARM gem5 Developers MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass) 9210037SARM gem5 Developers : ArmStaticInst(mnem, machInst, __opClass) 9310037SARM gem5 Developers {} 9410037SARM gem5 Developers 9510037SARM gem5 Developers public: 9610037SARM gem5 Developers void 9710037SARM gem5 Developers advancePC(PCState &pcState) const 9810037SARM gem5 Developers { 9910037SARM gem5 Developers if (flags[IsLastMicroop]) { 10010037SARM gem5 Developers pcState.uEnd(); 10110037SARM gem5 Developers } else if (flags[IsMicroop]) { 10210037SARM gem5 Developers pcState.uAdvance(); 10310037SARM gem5 Developers } else { 10410037SARM gem5 Developers pcState.advance(); 10510037SARM gem5 Developers } 10610037SARM gem5 Developers } 10710037SARM gem5 Developers}; 10810037SARM gem5 Developers 1096253Sgblack@eecs.umich.edu/** 1107639Sgblack@eecs.umich.edu * Microops for Neon loads/stores 1117639Sgblack@eecs.umich.edu */ 1127639Sgblack@eecs.umich.educlass MicroNeonMemOp : public MicroOp 1137639Sgblack@eecs.umich.edu{ 1147639Sgblack@eecs.umich.edu protected: 1157639Sgblack@eecs.umich.edu RegIndex dest, ura; 1167639Sgblack@eecs.umich.edu uint32_t imm; 1177639Sgblack@eecs.umich.edu unsigned memAccessFlags; 1187639Sgblack@eecs.umich.edu 1197639Sgblack@eecs.umich.edu MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1207639Sgblack@eecs.umich.edu RegIndex _dest, RegIndex _ura, uint32_t _imm) 1217639Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 1227639Sgblack@eecs.umich.edu dest(_dest), ura(_ura), imm(_imm), 1237639Sgblack@eecs.umich.edu memAccessFlags(TLB::MustBeOne) 1247639Sgblack@eecs.umich.edu { 1257639Sgblack@eecs.umich.edu } 1267639Sgblack@eecs.umich.edu}; 1277639Sgblack@eecs.umich.edu 1287639Sgblack@eecs.umich.edu/** 1297639Sgblack@eecs.umich.edu * Microops for Neon load/store (de)interleaving 1307639Sgblack@eecs.umich.edu */ 1317639Sgblack@eecs.umich.educlass MicroNeonMixOp : public MicroOp 1327639Sgblack@eecs.umich.edu{ 1337639Sgblack@eecs.umich.edu protected: 1347639Sgblack@eecs.umich.edu RegIndex dest, op1; 1357639Sgblack@eecs.umich.edu uint32_t step; 1367639Sgblack@eecs.umich.edu 1377639Sgblack@eecs.umich.edu MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1387639Sgblack@eecs.umich.edu RegIndex _dest, RegIndex _op1, uint32_t _step) 1397639Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 1407639Sgblack@eecs.umich.edu dest(_dest), op1(_op1), step(_step) 1417639Sgblack@eecs.umich.edu { 1427639Sgblack@eecs.umich.edu } 1437639Sgblack@eecs.umich.edu}; 1447639Sgblack@eecs.umich.edu 1457639Sgblack@eecs.umich.educlass MicroNeonMixLaneOp : public MicroNeonMixOp 1467639Sgblack@eecs.umich.edu{ 1477639Sgblack@eecs.umich.edu protected: 1487639Sgblack@eecs.umich.edu unsigned lane; 1497639Sgblack@eecs.umich.edu 1507639Sgblack@eecs.umich.edu MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 1517639Sgblack@eecs.umich.edu OpClass __opClass, RegIndex _dest, RegIndex _op1, 1527639Sgblack@eecs.umich.edu uint32_t _step, unsigned _lane) 1537639Sgblack@eecs.umich.edu : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 1547639Sgblack@eecs.umich.edu lane(_lane) 1557639Sgblack@eecs.umich.edu { 1567639Sgblack@eecs.umich.edu } 1577639Sgblack@eecs.umich.edu}; 1588140SMatt.Horsnell@arm.com 1598140SMatt.Horsnell@arm.com/** 16010037SARM gem5 Developers * Microops for AArch64 NEON load/store (de)interleaving 16110037SARM gem5 Developers */ 16210037SARM gem5 Developersclass MicroNeonMixOp64 : public MicroOp 16310037SARM gem5 Developers{ 16410037SARM gem5 Developers protected: 16510037SARM gem5 Developers RegIndex dest, op1; 16610037SARM gem5 Developers uint8_t eSize, dataSize, numStructElems, numRegs, step; 16710037SARM gem5 Developers 16810037SARM gem5 Developers MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 16910037SARM gem5 Developers RegIndex _dest, RegIndex _op1, uint8_t _eSize, 17010037SARM gem5 Developers uint8_t _dataSize, uint8_t _numStructElems, 17110037SARM gem5 Developers uint8_t _numRegs, uint8_t _step) 17210037SARM gem5 Developers : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1), 17310037SARM gem5 Developers eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems), 17410037SARM gem5 Developers numRegs(_numRegs), step(_step) 17510037SARM gem5 Developers { 17610037SARM gem5 Developers } 17710037SARM gem5 Developers}; 17810037SARM gem5 Developers 17910037SARM gem5 Developersclass MicroNeonMixLaneOp64 : public MicroOp 18010037SARM gem5 Developers{ 18110037SARM gem5 Developers protected: 18210037SARM gem5 Developers RegIndex dest, op1; 18310037SARM gem5 Developers uint8_t eSize, dataSize, numStructElems, lane, step; 18410037SARM gem5 Developers bool replicate; 18510037SARM gem5 Developers 18610037SARM gem5 Developers MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst, 18710037SARM gem5 Developers OpClass __opClass, RegIndex _dest, RegIndex _op1, 18810037SARM gem5 Developers uint8_t _eSize, uint8_t _dataSize, 18910037SARM gem5 Developers uint8_t _numStructElems, uint8_t _lane, uint8_t _step, 19010037SARM gem5 Developers bool _replicate = false) 19110037SARM gem5 Developers : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1), 19210037SARM gem5 Developers eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems), 19310037SARM gem5 Developers lane(_lane), step(_step), replicate(_replicate) 19410037SARM gem5 Developers { 19510037SARM gem5 Developers } 19610037SARM gem5 Developers}; 19710037SARM gem5 Developers 19810037SARM gem5 Developers/** 19910037SARM gem5 Developers * Base classes for microcoded AArch64 NEON memory instructions. 20010037SARM gem5 Developers */ 20110037SARM gem5 Developersclass VldMultOp64 : public PredMacroOp 20210037SARM gem5 Developers{ 20310037SARM gem5 Developers protected: 20410037SARM gem5 Developers uint8_t eSize, dataSize, numStructElems, numRegs; 20510037SARM gem5 Developers bool wb; 20610037SARM gem5 Developers 20710037SARM gem5 Developers VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 20810037SARM gem5 Developers RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 20910037SARM gem5 Developers uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, 21010037SARM gem5 Developers bool wb); 21110037SARM gem5 Developers}; 21210037SARM gem5 Developers 21310037SARM gem5 Developersclass VstMultOp64 : public PredMacroOp 21410037SARM gem5 Developers{ 21510037SARM gem5 Developers protected: 21610037SARM gem5 Developers uint8_t eSize, dataSize, numStructElems, numRegs; 21710037SARM gem5 Developers bool wb; 21810037SARM gem5 Developers 21910037SARM gem5 Developers VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 22010037SARM gem5 Developers RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 22110037SARM gem5 Developers uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, 22210037SARM gem5 Developers bool wb); 22310037SARM gem5 Developers}; 22410037SARM gem5 Developers 22510037SARM gem5 Developersclass VldSingleOp64 : public PredMacroOp 22610037SARM gem5 Developers{ 22710037SARM gem5 Developers protected: 22810037SARM gem5 Developers uint8_t eSize, dataSize, numStructElems, index; 22910037SARM gem5 Developers bool wb, replicate; 23010037SARM gem5 Developers 23110037SARM gem5 Developers VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 23210037SARM gem5 Developers RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 23310037SARM gem5 Developers uint8_t dataSize, uint8_t numStructElems, uint8_t index, 23410037SARM gem5 Developers bool wb, bool replicate = false); 23510037SARM gem5 Developers}; 23610037SARM gem5 Developers 23710037SARM gem5 Developersclass VstSingleOp64 : public PredMacroOp 23810037SARM gem5 Developers{ 23910037SARM gem5 Developers protected: 24010037SARM gem5 Developers uint8_t eSize, dataSize, numStructElems, index; 24110037SARM gem5 Developers bool wb, replicate; 24210037SARM gem5 Developers 24310037SARM gem5 Developers VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 24410037SARM gem5 Developers RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 24510037SARM gem5 Developers uint8_t dataSize, uint8_t numStructElems, uint8_t index, 24610037SARM gem5 Developers bool wb, bool replicate = false); 24710037SARM gem5 Developers}; 24810037SARM gem5 Developers 24910037SARM gem5 Developers/** 2508140SMatt.Horsnell@arm.com * Microops of the form 2518140SMatt.Horsnell@arm.com * PC = IntRegA 2528140SMatt.Horsnell@arm.com * CPSR = IntRegB 2538140SMatt.Horsnell@arm.com */ 2548140SMatt.Horsnell@arm.comclass MicroSetPCCPSR : public MicroOp 2558140SMatt.Horsnell@arm.com{ 2568140SMatt.Horsnell@arm.com protected: 2578140SMatt.Horsnell@arm.com IntRegIndex ura, urb, urc; 2588140SMatt.Horsnell@arm.com 2598140SMatt.Horsnell@arm.com MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2608140SMatt.Horsnell@arm.com IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) 2618140SMatt.Horsnell@arm.com : MicroOp(mnem, machInst, __opClass), 2628140SMatt.Horsnell@arm.com ura(_ura), urb(_urb), urc(_urc) 2638140SMatt.Horsnell@arm.com { 2648140SMatt.Horsnell@arm.com } 2658140SMatt.Horsnell@arm.com 2668140SMatt.Horsnell@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2678140SMatt.Horsnell@arm.com}; 2688140SMatt.Horsnell@arm.com 2697646Sgene.wu@arm.com/** 2707646Sgene.wu@arm.com * Microops of the form IntRegA = IntRegB 2717646Sgene.wu@arm.com */ 2727646Sgene.wu@arm.comclass MicroIntMov : public MicroOp 2737646Sgene.wu@arm.com{ 2747646Sgene.wu@arm.com protected: 2757646Sgene.wu@arm.com RegIndex ura, urb; 2767646Sgene.wu@arm.com 2777646Sgene.wu@arm.com MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, 2787646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb) 2797646Sgene.wu@arm.com : MicroOp(mnem, machInst, __opClass), 2807646Sgene.wu@arm.com ura(_ura), urb(_urb) 2817646Sgene.wu@arm.com { 2827646Sgene.wu@arm.com } 2837646Sgene.wu@arm.com 2847646Sgene.wu@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2857646Sgene.wu@arm.com}; 2867639Sgblack@eecs.umich.edu 2877639Sgblack@eecs.umich.edu/** 2886308Sgblack@eecs.umich.edu * Microops of the form IntRegA = IntRegB op Imm 2896308Sgblack@eecs.umich.edu */ 2907639Sgblack@eecs.umich.educlass MicroIntImmOp : public MicroOp 2916308Sgblack@eecs.umich.edu{ 2926308Sgblack@eecs.umich.edu protected: 2936308Sgblack@eecs.umich.edu RegIndex ura, urb; 29410037SARM gem5 Developers int32_t imm; 2956308Sgblack@eecs.umich.edu 2967639Sgblack@eecs.umich.edu MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 29710037SARM gem5 Developers RegIndex _ura, RegIndex _urb, int32_t _imm) 2987343Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 2996308Sgblack@eecs.umich.edu ura(_ura), urb(_urb), imm(_imm) 3006308Sgblack@eecs.umich.edu { 3016308Sgblack@eecs.umich.edu } 3027615Sminkyu.jeong@arm.com 3037615Sminkyu.jeong@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 3046308Sgblack@eecs.umich.edu}; 3056308Sgblack@eecs.umich.edu 30610037SARM gem5 Developersclass MicroIntImmXOp : public MicroOpX 30710037SARM gem5 Developers{ 30810037SARM gem5 Developers protected: 30910037SARM gem5 Developers RegIndex ura, urb; 31010037SARM gem5 Developers int64_t imm; 31110037SARM gem5 Developers 31210037SARM gem5 Developers MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 31310037SARM gem5 Developers RegIndex _ura, RegIndex _urb, int64_t _imm) 31410037SARM gem5 Developers : MicroOpX(mnem, machInst, __opClass), 31510037SARM gem5 Developers ura(_ura), urb(_urb), imm(_imm) 31610037SARM gem5 Developers { 31710037SARM gem5 Developers } 31810037SARM gem5 Developers 31910037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 32010037SARM gem5 Developers}; 32110037SARM gem5 Developers 3226308Sgblack@eecs.umich.edu/** 3237639Sgblack@eecs.umich.edu * Microops of the form IntRegA = IntRegB op IntRegC 3247639Sgblack@eecs.umich.edu */ 3257639Sgblack@eecs.umich.educlass MicroIntOp : public MicroOp 3267639Sgblack@eecs.umich.edu{ 3277639Sgblack@eecs.umich.edu protected: 3287639Sgblack@eecs.umich.edu RegIndex ura, urb, urc; 3297639Sgblack@eecs.umich.edu 3307639Sgblack@eecs.umich.edu MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 3317639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc) 3327639Sgblack@eecs.umich.edu : MicroOp(mnem, machInst, __opClass), 3337639Sgblack@eecs.umich.edu ura(_ura), urb(_urb), urc(_urc) 3347639Sgblack@eecs.umich.edu { 3357639Sgblack@eecs.umich.edu } 3367639Sgblack@eecs.umich.edu 3377639Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 3387639Sgblack@eecs.umich.edu}; 3397639Sgblack@eecs.umich.edu 34010037SARM gem5 Developersclass MicroIntRegXOp : public MicroOp 34110037SARM gem5 Developers{ 34210037SARM gem5 Developers protected: 34310037SARM gem5 Developers RegIndex ura, urb, urc; 34410037SARM gem5 Developers ArmExtendType type; 34510037SARM gem5 Developers uint32_t shiftAmt; 34610037SARM gem5 Developers 34710037SARM gem5 Developers MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 34810037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 34910037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt) 35010037SARM gem5 Developers : MicroOp(mnem, machInst, __opClass), 35110037SARM gem5 Developers ura(_ura), urb(_urb), urc(_urc), 35210037SARM gem5 Developers type(_type), shiftAmt(_shiftAmt) 35310037SARM gem5 Developers { 35410037SARM gem5 Developers } 35510037SARM gem5 Developers 35610037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 35710037SARM gem5 Developers}; 35810037SARM gem5 Developers 3597639Sgblack@eecs.umich.edu/** 3607646Sgene.wu@arm.com * Microops of the form IntRegA = IntRegB op shifted IntRegC 3617646Sgene.wu@arm.com */ 3627646Sgene.wu@arm.comclass MicroIntRegOp : public MicroOp 3637646Sgene.wu@arm.com{ 3647646Sgene.wu@arm.com protected: 3657646Sgene.wu@arm.com RegIndex ura, urb, urc; 3667646Sgene.wu@arm.com int32_t shiftAmt; 3677646Sgene.wu@arm.com ArmShiftType shiftType; 3687646Sgene.wu@arm.com 3697646Sgene.wu@arm.com MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 3707646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3717646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 3727646Sgene.wu@arm.com : MicroOp(mnem, machInst, __opClass), 3737646Sgene.wu@arm.com ura(_ura), urb(_urb), urc(_urc), 3747646Sgene.wu@arm.com shiftAmt(_shiftAmt), shiftType(_shiftType) 3757646Sgene.wu@arm.com { 3767646Sgene.wu@arm.com } 3777646Sgene.wu@arm.com}; 3787646Sgene.wu@arm.com 3797646Sgene.wu@arm.com/** 3806309Sgblack@eecs.umich.edu * Memory microops which use IntReg + Imm addressing 3816309Sgblack@eecs.umich.edu */ 3827639Sgblack@eecs.umich.educlass MicroMemOp : public MicroIntImmOp 3836309Sgblack@eecs.umich.edu{ 3846309Sgblack@eecs.umich.edu protected: 3857134Sgblack@eecs.umich.edu bool up; 3866309Sgblack@eecs.umich.edu unsigned memAccessFlags; 3876309Sgblack@eecs.umich.edu 3886309Sgblack@eecs.umich.edu MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 3897134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 3907639Sgblack@eecs.umich.edu : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 3917294Sgblack@eecs.umich.edu up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 3926309Sgblack@eecs.umich.edu { 3936309Sgblack@eecs.umich.edu } 3947615Sminkyu.jeong@arm.com 3957615Sminkyu.jeong@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 3966309Sgblack@eecs.umich.edu}; 3976309Sgblack@eecs.umich.edu 3987431Sgblack@eecs.umich.edu/** 3997431Sgblack@eecs.umich.edu * Base class for microcoded integer memory instructions. 4007431Sgblack@eecs.umich.edu */ 4017170Sgblack@eecs.umich.educlass MacroMemOp : public PredMacroOp 4027170Sgblack@eecs.umich.edu{ 4037170Sgblack@eecs.umich.edu protected: 4047170Sgblack@eecs.umich.edu MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 4057170Sgblack@eecs.umich.edu IntRegIndex rn, bool index, bool up, bool user, 4067170Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t reglist); 4077170Sgblack@eecs.umich.edu}; 4087170Sgblack@eecs.umich.edu 4097431Sgblack@eecs.umich.edu/** 41010037SARM gem5 Developers * Base class for pair load/store instructions. 41110037SARM gem5 Developers */ 41210037SARM gem5 Developersclass PairMemOp : public PredMacroOp 41310037SARM gem5 Developers{ 41410037SARM gem5 Developers public: 41510037SARM gem5 Developers enum AddrMode { 41610037SARM gem5 Developers AddrMd_Offset, 41710037SARM gem5 Developers AddrMd_PreIndex, 41810037SARM gem5 Developers AddrMd_PostIndex 41910037SARM gem5 Developers }; 42010037SARM gem5 Developers 42110037SARM gem5 Developers protected: 42210037SARM gem5 Developers PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 42310037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 42410037SARM gem5 Developers bool exclusive, bool acrel, int64_t imm, AddrMode mode, 42510037SARM gem5 Developers IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2); 42610037SARM gem5 Developers}; 42710037SARM gem5 Developers 42810037SARM gem5 Developersclass BigFpMemImmOp : public PredMacroOp 42910037SARM gem5 Developers{ 43010037SARM gem5 Developers protected: 43110037SARM gem5 Developers BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 43210037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 43310037SARM gem5 Developers}; 43410037SARM gem5 Developers 43510037SARM gem5 Developersclass BigFpMemPostOp : public PredMacroOp 43610037SARM gem5 Developers{ 43710037SARM gem5 Developers protected: 43810037SARM gem5 Developers BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 43910037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 44010037SARM gem5 Developers}; 44110037SARM gem5 Developers 44210037SARM gem5 Developersclass BigFpMemPreOp : public PredMacroOp 44310037SARM gem5 Developers{ 44410037SARM gem5 Developers protected: 44510037SARM gem5 Developers BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 44610037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 44710037SARM gem5 Developers}; 44810037SARM gem5 Developers 44910037SARM gem5 Developersclass BigFpMemRegOp : public PredMacroOp 45010037SARM gem5 Developers{ 45110037SARM gem5 Developers protected: 45210037SARM gem5 Developers BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 45310037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 45410037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm); 45510037SARM gem5 Developers}; 45610037SARM gem5 Developers 45710037SARM gem5 Developersclass BigFpMemLitOp : public PredMacroOp 45810037SARM gem5 Developers{ 45910037SARM gem5 Developers protected: 46010037SARM gem5 Developers BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 46110037SARM gem5 Developers IntRegIndex dest, int64_t imm); 46210037SARM gem5 Developers}; 46310037SARM gem5 Developers 46410037SARM gem5 Developers/** 4657639Sgblack@eecs.umich.edu * Base classes for microcoded integer memory instructions. 4667639Sgblack@eecs.umich.edu */ 4677639Sgblack@eecs.umich.educlass VldMultOp : public PredMacroOp 4687639Sgblack@eecs.umich.edu{ 4697639Sgblack@eecs.umich.edu protected: 4707639Sgblack@eecs.umich.edu VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 4717639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 4727639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 4737639Sgblack@eecs.umich.edu}; 4747639Sgblack@eecs.umich.edu 4757639Sgblack@eecs.umich.educlass VldSingleOp : public PredMacroOp 4767639Sgblack@eecs.umich.edu{ 4777639Sgblack@eecs.umich.edu protected: 4787639Sgblack@eecs.umich.edu VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 4797639Sgblack@eecs.umich.edu bool all, unsigned elems, RegIndex rn, RegIndex vd, 4807639Sgblack@eecs.umich.edu unsigned regs, unsigned inc, uint32_t size, 4817639Sgblack@eecs.umich.edu uint32_t align, RegIndex rm, unsigned lane); 4827639Sgblack@eecs.umich.edu}; 4837639Sgblack@eecs.umich.edu 4847639Sgblack@eecs.umich.edu/** 4857639Sgblack@eecs.umich.edu * Base class for microcoded integer memory instructions. 4867639Sgblack@eecs.umich.edu */ 4877639Sgblack@eecs.umich.educlass VstMultOp : public PredMacroOp 4887639Sgblack@eecs.umich.edu{ 4897639Sgblack@eecs.umich.edu protected: 4907639Sgblack@eecs.umich.edu VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 4917639Sgblack@eecs.umich.edu unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 4927639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 4937639Sgblack@eecs.umich.edu}; 4947639Sgblack@eecs.umich.edu 4957639Sgblack@eecs.umich.educlass VstSingleOp : public PredMacroOp 4967639Sgblack@eecs.umich.edu{ 4977639Sgblack@eecs.umich.edu protected: 4987639Sgblack@eecs.umich.edu VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 4997639Sgblack@eecs.umich.edu bool all, unsigned elems, RegIndex rn, RegIndex vd, 5007639Sgblack@eecs.umich.edu unsigned regs, unsigned inc, uint32_t size, 5017639Sgblack@eecs.umich.edu uint32_t align, RegIndex rm, unsigned lane); 5027639Sgblack@eecs.umich.edu}; 5037639Sgblack@eecs.umich.edu 5047639Sgblack@eecs.umich.edu/** 5057431Sgblack@eecs.umich.edu * Base class for microcoded floating point memory instructions. 5067431Sgblack@eecs.umich.edu */ 5077175Sgblack@eecs.umich.educlass MacroVFPMemOp : public PredMacroOp 5087175Sgblack@eecs.umich.edu{ 5097175Sgblack@eecs.umich.edu protected: 5107175Sgblack@eecs.umich.edu MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 5117175Sgblack@eecs.umich.edu IntRegIndex rn, RegIndex vd, bool single, bool up, 5127175Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t offset); 5137175Sgblack@eecs.umich.edu}; 5147175Sgblack@eecs.umich.edu 5156253Sgblack@eecs.umich.edu} 5166253Sgblack@eecs.umich.edu 5176253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ 518