macromem.cc revision 9250
17170Sgblack@eecs.umich.edu/* 27170Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37170Sgblack@eecs.umich.edu * All rights reserved 47170Sgblack@eecs.umich.edu * 57170Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67170Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77170Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87170Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97170Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107170Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117170Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127170Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137170Sgblack@eecs.umich.edu * 147170Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 157170Sgblack@eecs.umich.edu * All rights reserved. 167170Sgblack@eecs.umich.edu * 177170Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187170Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197170Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217170Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237170Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247170Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257170Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267170Sgblack@eecs.umich.edu * this software without specific prior written permission. 277170Sgblack@eecs.umich.edu * 287170Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297170Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307170Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317170Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327170Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337170Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347170Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357170Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367170Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377170Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387170Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397170Sgblack@eecs.umich.edu * 407170Sgblack@eecs.umich.edu * Authors: Stephen Hines 417170Sgblack@eecs.umich.edu */ 427170Sgblack@eecs.umich.edu 438229Snate@binkert.org#include <sstream> 448229Snate@binkert.org 457170Sgblack@eecs.umich.edu#include "arch/arm/insts/macromem.hh" 468961Sgblack@eecs.umich.edu#include "arch/arm/generated/decoder.hh" 477170Sgblack@eecs.umich.edu 487853SMatt.Horsnell@ARM.comusing namespace std; 497170Sgblack@eecs.umich.eduusing namespace ArmISAInst; 507170Sgblack@eecs.umich.edu 517170Sgblack@eecs.umich.edunamespace ArmISA 527170Sgblack@eecs.umich.edu{ 537170Sgblack@eecs.umich.edu 547170Sgblack@eecs.umich.eduMacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, 557170Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 567170Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, 577170Sgblack@eecs.umich.edu bool load, uint32_t reglist) : 587170Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 597170Sgblack@eecs.umich.edu{ 607170Sgblack@eecs.umich.edu uint32_t regs = reglist; 617170Sgblack@eecs.umich.edu uint32_t ones = number_of_ones(reglist); 628148SAli.Saidi@ARM.com // Remember that writeback adds a uop or two and the temp register adds one 638148SAli.Saidi@ARM.com numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1; 648148SAli.Saidi@ARM.com 658148SAli.Saidi@ARM.com // It's technically legal to do a lot of nothing 668148SAli.Saidi@ARM.com if (!ones) 678148SAli.Saidi@ARM.com numMicroops = 1; 688148SAli.Saidi@ARM.com 697170Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 707170Sgblack@eecs.umich.edu uint32_t addr = 0; 717170Sgblack@eecs.umich.edu 727170Sgblack@eecs.umich.edu if (!up) 737170Sgblack@eecs.umich.edu addr = (ones << 2) - 4; 747170Sgblack@eecs.umich.edu 757170Sgblack@eecs.umich.edu if (!index) 767170Sgblack@eecs.umich.edu addr += 4; 777170Sgblack@eecs.umich.edu 787190Sgblack@eecs.umich.edu StaticInstPtr *uop = microOps; 797190Sgblack@eecs.umich.edu 807170Sgblack@eecs.umich.edu // Add 0 to Rn and stick it in ureg0. 817170Sgblack@eecs.umich.edu // This is equivalent to a move. 827190Sgblack@eecs.umich.edu *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0); 837190Sgblack@eecs.umich.edu 847170Sgblack@eecs.umich.edu unsigned reg = 0; 858148SAli.Saidi@ARM.com unsigned regIdx = 0; 867170Sgblack@eecs.umich.edu bool force_user = user & !bits(reglist, 15); 877170Sgblack@eecs.umich.edu bool exception_ret = user & bits(reglist, 15); 887170Sgblack@eecs.umich.edu 897190Sgblack@eecs.umich.edu for (int i = 0; i < ones; i++) { 907170Sgblack@eecs.umich.edu // Find the next register. 917170Sgblack@eecs.umich.edu while (!bits(regs, reg)) 927170Sgblack@eecs.umich.edu reg++; 937170Sgblack@eecs.umich.edu replaceBits(regs, reg, 0); 947170Sgblack@eecs.umich.edu 958148SAli.Saidi@ARM.com regIdx = reg; 967170Sgblack@eecs.umich.edu if (force_user) { 977310Sgblack@eecs.umich.edu regIdx = intRegInMode(MODE_USER, regIdx); 987170Sgblack@eecs.umich.edu } 997170Sgblack@eecs.umich.edu 1007170Sgblack@eecs.umich.edu if (load) { 1018148SAli.Saidi@ARM.com if (writeback && i == ones - 1) { 1028148SAli.Saidi@ARM.com // If it's a writeback and this is the last register 1038148SAli.Saidi@ARM.com // do the load into a temporary register which we'll move 1048148SAli.Saidi@ARM.com // into the final one later 1058148SAli.Saidi@ARM.com *++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0, 1068148SAli.Saidi@ARM.com up, addr); 1077170Sgblack@eecs.umich.edu } else { 1088148SAli.Saidi@ARM.com // Otherwise just do it normally 1098148SAli.Saidi@ARM.com if (reg == INTREG_PC && exception_ret) { 1108148SAli.Saidi@ARM.com // This must be the exception return form of ldm. 1118148SAli.Saidi@ARM.com *++uop = new MicroLdrRetUop(machInst, regIdx, 1128148SAli.Saidi@ARM.com INTREG_UREG0, up, addr); 1138148SAli.Saidi@ARM.com } else { 1148148SAli.Saidi@ARM.com *++uop = new MicroLdrUop(machInst, regIdx, 1158148SAli.Saidi@ARM.com INTREG_UREG0, up, addr); 1169250SAli.Saidi@ARM.com if (reg == INTREG_PC) { 1179250SAli.Saidi@ARM.com (*uop)->setFlag(StaticInst::IsControl); 1189250SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) 1199250SAli.Saidi@ARM.com (*uop)->setFlag(StaticInst::IsCondControl); 1209250SAli.Saidi@ARM.com else 1219250SAli.Saidi@ARM.com (*uop)->setFlag(StaticInst::IsUncondControl); 1229250SAli.Saidi@ARM.com (*uop)->setFlag(StaticInst::IsIndirectControl); 1239250SAli.Saidi@ARM.com } 1248148SAli.Saidi@ARM.com } 1257170Sgblack@eecs.umich.edu } 1267170Sgblack@eecs.umich.edu } else { 1277190Sgblack@eecs.umich.edu *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr); 1287170Sgblack@eecs.umich.edu } 1297170Sgblack@eecs.umich.edu 1307170Sgblack@eecs.umich.edu if (up) 1317170Sgblack@eecs.umich.edu addr += 4; 1327170Sgblack@eecs.umich.edu else 1337170Sgblack@eecs.umich.edu addr -= 4; 1347170Sgblack@eecs.umich.edu } 1357170Sgblack@eecs.umich.edu 1368148SAli.Saidi@ARM.com if (writeback && ones) { 1378148SAli.Saidi@ARM.com // put the register update after we're done all loading 1388148SAli.Saidi@ARM.com if (up) 1398148SAli.Saidi@ARM.com *++uop = new MicroAddiUop(machInst, rn, rn, ones * 4); 1408148SAli.Saidi@ARM.com else 1418148SAli.Saidi@ARM.com *++uop = new MicroSubiUop(machInst, rn, rn, ones * 4); 1428148SAli.Saidi@ARM.com 1438148SAli.Saidi@ARM.com // If this was a load move the last temporary value into place 1448148SAli.Saidi@ARM.com // this way we can't take an exception after we update the base 1458148SAli.Saidi@ARM.com // register. 1468148SAli.Saidi@ARM.com if (load && reg == INTREG_PC && exception_ret) { 1478148SAli.Saidi@ARM.com *++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1); 1488148SAli.Saidi@ARM.com } else if (load) { 1498148SAli.Saidi@ARM.com *++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1); 1508148SAli.Saidi@ARM.com if (reg == INTREG_PC) { 1518542Sgblack@eecs.umich.edu (*uop)->setFlag(StaticInst::IsControl); 1528542Sgblack@eecs.umich.edu (*uop)->setFlag(StaticInst::IsCondControl); 1538542Sgblack@eecs.umich.edu (*uop)->setFlag(StaticInst::IsIndirectControl); 1548148SAli.Saidi@ARM.com // This is created as a RAS POP 1558148SAli.Saidi@ARM.com if (rn == INTREG_SP) 1568542Sgblack@eecs.umich.edu (*uop)->setFlag(StaticInst::IsReturn); 1578148SAli.Saidi@ARM.com 1588148SAli.Saidi@ARM.com } 1598148SAli.Saidi@ARM.com } 1607170Sgblack@eecs.umich.edu } 1617190Sgblack@eecs.umich.edu 1627190Sgblack@eecs.umich.edu (*uop)->setLastMicroop(); 1637343Sgblack@eecs.umich.edu 1647343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 1657343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 1667343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 1677343Sgblack@eecs.umich.edu assert(uopPtr); 1687343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 1697343Sgblack@eecs.umich.edu } 1707170Sgblack@eecs.umich.edu} 1717170Sgblack@eecs.umich.edu 1727639Sgblack@eecs.umich.eduVldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1737639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 1747639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 1757639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 1767639Sgblack@eecs.umich.edu{ 1777639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 1787639Sgblack@eecs.umich.edu assert(regs % elems == 0); 1797639Sgblack@eecs.umich.edu 1807639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 1817639Sgblack@eecs.umich.edu bool wb = (rm != 15); 1827639Sgblack@eecs.umich.edu bool deinterleave = (elems > 1); 1837639Sgblack@eecs.umich.edu 1847639Sgblack@eecs.umich.edu if (wb) numMicroops++; 1857639Sgblack@eecs.umich.edu if (deinterleave) numMicroops += (regs / elems); 1867639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1877639Sgblack@eecs.umich.edu 1887639Sgblack@eecs.umich.edu RegIndex rMid = deinterleave ? NumFloatArchRegs : vd * 2; 1897639Sgblack@eecs.umich.edu 1907639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 1917639Sgblack@eecs.umich.edu 1927639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 1937639Sgblack@eecs.umich.edu switch (regs) { 1947639Sgblack@eecs.umich.edu case 4: 1957639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1967639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1977639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1987639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1997639Sgblack@eecs.umich.edu break; 2007639Sgblack@eecs.umich.edu case 3: 2017639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 2027639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 2037639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 2047639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 2057639Sgblack@eecs.umich.edu break; 2067639Sgblack@eecs.umich.edu case 2: 2077639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 2087639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 2097639Sgblack@eecs.umich.edu break; 2107639Sgblack@eecs.umich.edu case 1: 2117639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 2127639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 2137639Sgblack@eecs.umich.edu break; 2147639Sgblack@eecs.umich.edu default: 2157853SMatt.Horsnell@ARM.com // Unknown number of registers 2167853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 2177639Sgblack@eecs.umich.edu } 2187639Sgblack@eecs.umich.edu if (wb) { 2197639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 2207639Sgblack@eecs.umich.edu microOps[uopIdx++] = 2217646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 2227639Sgblack@eecs.umich.edu } else { 2237639Sgblack@eecs.umich.edu microOps[uopIdx++] = 2247639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 2257639Sgblack@eecs.umich.edu } 2267639Sgblack@eecs.umich.edu } 2277639Sgblack@eecs.umich.edu if (deinterleave) { 2287639Sgblack@eecs.umich.edu switch (elems) { 2297639Sgblack@eecs.umich.edu case 4: 2307639Sgblack@eecs.umich.edu assert(regs == 4); 2317639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon8Uop>( 2327639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2337639Sgblack@eecs.umich.edu break; 2347639Sgblack@eecs.umich.edu case 3: 2357639Sgblack@eecs.umich.edu assert(regs == 3); 2367639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon6Uop>( 2377639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2387639Sgblack@eecs.umich.edu break; 2397639Sgblack@eecs.umich.edu case 2: 2407639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 2417639Sgblack@eecs.umich.edu if (regs == 4) { 2427639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2437639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2447639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2457639Sgblack@eecs.umich.edu size, machInst, vd * 2 + 2, rMid + 4, inc * 2); 2467639Sgblack@eecs.umich.edu } else { 2477639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2487639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2497639Sgblack@eecs.umich.edu } 2507639Sgblack@eecs.umich.edu break; 2517639Sgblack@eecs.umich.edu default: 2527853SMatt.Horsnell@ARM.com // Bad number of elements to deinterleave 2537853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 2547639Sgblack@eecs.umich.edu } 2557639Sgblack@eecs.umich.edu } 2567639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 2577639Sgblack@eecs.umich.edu 2587639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 2597639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 2607639Sgblack@eecs.umich.edu assert(uopPtr); 2617639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 2627639Sgblack@eecs.umich.edu } 2637639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 2647639Sgblack@eecs.umich.edu} 2657639Sgblack@eecs.umich.edu 2667639Sgblack@eecs.umich.eduVldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, 2677639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 2687639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 2697639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 2707639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 2717639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 2727639Sgblack@eecs.umich.edu{ 2737639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 2747639Sgblack@eecs.umich.edu assert(regs % elems == 0); 2757639Sgblack@eecs.umich.edu 2767639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 2777639Sgblack@eecs.umich.edu unsigned loadSize = eBytes * elems; 2787639Sgblack@eecs.umich.edu unsigned loadRegs M5_VAR_USED = (loadSize + sizeof(FloatRegBits) - 1) / 2797639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 2807639Sgblack@eecs.umich.edu 2817639Sgblack@eecs.umich.edu assert(loadRegs > 0 && loadRegs <= 4); 2827639Sgblack@eecs.umich.edu 2837639Sgblack@eecs.umich.edu numMicroops = 1; 2847639Sgblack@eecs.umich.edu bool wb = (rm != 15); 2857639Sgblack@eecs.umich.edu 2867639Sgblack@eecs.umich.edu if (wb) numMicroops++; 2877639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 2887639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 2897639Sgblack@eecs.umich.edu 2907639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 2917639Sgblack@eecs.umich.edu 2927639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 2937639Sgblack@eecs.umich.edu switch (loadSize) { 2947639Sgblack@eecs.umich.edu case 1: 2957639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon1Uop<uint8_t>( 2967639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2977639Sgblack@eecs.umich.edu break; 2987639Sgblack@eecs.umich.edu case 2: 2997639Sgblack@eecs.umich.edu if (eBytes == 2) { 3007639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint16_t>( 3017639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3027639Sgblack@eecs.umich.edu } else { 3037639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint8_t>( 3047639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3057639Sgblack@eecs.umich.edu } 3067639Sgblack@eecs.umich.edu break; 3077639Sgblack@eecs.umich.edu case 3: 3087639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon3Uop<uint8_t>( 3097639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3107639Sgblack@eecs.umich.edu break; 3117639Sgblack@eecs.umich.edu case 4: 3127639Sgblack@eecs.umich.edu switch (eBytes) { 3137639Sgblack@eecs.umich.edu case 1: 3147639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint8_t>( 3157639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3167639Sgblack@eecs.umich.edu break; 3177639Sgblack@eecs.umich.edu case 2: 3187639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint16_t>( 3197639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3207639Sgblack@eecs.umich.edu break; 3217639Sgblack@eecs.umich.edu case 4: 3227639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint32_t>( 3237639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3247639Sgblack@eecs.umich.edu break; 3257639Sgblack@eecs.umich.edu } 3267639Sgblack@eecs.umich.edu break; 3277639Sgblack@eecs.umich.edu case 6: 3287639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon6Uop<uint16_t>( 3297639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3307639Sgblack@eecs.umich.edu break; 3317639Sgblack@eecs.umich.edu case 8: 3327639Sgblack@eecs.umich.edu switch (eBytes) { 3337639Sgblack@eecs.umich.edu case 2: 3347639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint16_t>( 3357639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3367639Sgblack@eecs.umich.edu break; 3377639Sgblack@eecs.umich.edu case 4: 3387639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint32_t>( 3397639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3407639Sgblack@eecs.umich.edu break; 3417639Sgblack@eecs.umich.edu } 3427639Sgblack@eecs.umich.edu break; 3437639Sgblack@eecs.umich.edu case 12: 3447639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon12Uop<uint32_t>( 3457639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3467639Sgblack@eecs.umich.edu break; 3477639Sgblack@eecs.umich.edu case 16: 3487639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon16Uop<uint32_t>( 3497639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3507639Sgblack@eecs.umich.edu break; 3517639Sgblack@eecs.umich.edu default: 3527853SMatt.Horsnell@ARM.com // Unrecognized load size 3537853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 3547639Sgblack@eecs.umich.edu } 3557639Sgblack@eecs.umich.edu if (wb) { 3567639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 3577639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3587646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 3597639Sgblack@eecs.umich.edu } else { 3607639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3617639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, loadSize); 3627639Sgblack@eecs.umich.edu } 3637639Sgblack@eecs.umich.edu } 3647639Sgblack@eecs.umich.edu switch (elems) { 3657639Sgblack@eecs.umich.edu case 4: 3667639Sgblack@eecs.umich.edu assert(regs == 4); 3677639Sgblack@eecs.umich.edu switch (size) { 3687639Sgblack@eecs.umich.edu case 0: 3697639Sgblack@eecs.umich.edu if (all) { 3707639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint8_t>( 3717639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3727639Sgblack@eecs.umich.edu } else { 3737639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint8_t>( 3747639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3757639Sgblack@eecs.umich.edu } 3767639Sgblack@eecs.umich.edu break; 3777639Sgblack@eecs.umich.edu case 1: 3787639Sgblack@eecs.umich.edu if (all) { 3797639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint16_t>( 3807639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3817639Sgblack@eecs.umich.edu } else { 3827639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint16_t>( 3837639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3847639Sgblack@eecs.umich.edu } 3857639Sgblack@eecs.umich.edu break; 3867639Sgblack@eecs.umich.edu case 2: 3877639Sgblack@eecs.umich.edu if (all) { 3887639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to8Uop<uint32_t>( 3897639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3907639Sgblack@eecs.umich.edu } else { 3917639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to8Uop<uint32_t>( 3927639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3937639Sgblack@eecs.umich.edu } 3947639Sgblack@eecs.umich.edu break; 3957639Sgblack@eecs.umich.edu default: 3967853SMatt.Horsnell@ARM.com // Bad size 3977853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 3987639Sgblack@eecs.umich.edu break; 3997639Sgblack@eecs.umich.edu } 4007639Sgblack@eecs.umich.edu break; 4017639Sgblack@eecs.umich.edu case 3: 4027639Sgblack@eecs.umich.edu assert(regs == 3); 4037639Sgblack@eecs.umich.edu switch (size) { 4047639Sgblack@eecs.umich.edu case 0: 4057639Sgblack@eecs.umich.edu if (all) { 4067639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint8_t>( 4077639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4087639Sgblack@eecs.umich.edu } else { 4097639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint8_t>( 4107639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4117639Sgblack@eecs.umich.edu } 4127639Sgblack@eecs.umich.edu break; 4137639Sgblack@eecs.umich.edu case 1: 4147639Sgblack@eecs.umich.edu if (all) { 4157639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint16_t>( 4167639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4177639Sgblack@eecs.umich.edu } else { 4187639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint16_t>( 4197639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4207639Sgblack@eecs.umich.edu } 4217639Sgblack@eecs.umich.edu break; 4227639Sgblack@eecs.umich.edu case 2: 4237639Sgblack@eecs.umich.edu if (all) { 4247639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to6Uop<uint32_t>( 4257639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4267639Sgblack@eecs.umich.edu } else { 4277639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to6Uop<uint32_t>( 4287639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4297639Sgblack@eecs.umich.edu } 4307639Sgblack@eecs.umich.edu break; 4317639Sgblack@eecs.umich.edu default: 4327853SMatt.Horsnell@ARM.com // Bad size 4337853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4347639Sgblack@eecs.umich.edu break; 4357639Sgblack@eecs.umich.edu } 4367639Sgblack@eecs.umich.edu break; 4377639Sgblack@eecs.umich.edu case 2: 4387639Sgblack@eecs.umich.edu assert(regs == 2); 4397639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4407639Sgblack@eecs.umich.edu switch (size) { 4417639Sgblack@eecs.umich.edu case 0: 4427639Sgblack@eecs.umich.edu if (all) { 4437639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint8_t>( 4447639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4457639Sgblack@eecs.umich.edu } else { 4467639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint8_t>( 4477639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4487639Sgblack@eecs.umich.edu } 4497639Sgblack@eecs.umich.edu break; 4507639Sgblack@eecs.umich.edu case 1: 4517639Sgblack@eecs.umich.edu if (all) { 4527639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint16_t>( 4537639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4547639Sgblack@eecs.umich.edu } else { 4557639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint16_t>( 4567639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4577639Sgblack@eecs.umich.edu } 4587639Sgblack@eecs.umich.edu break; 4597639Sgblack@eecs.umich.edu case 2: 4607639Sgblack@eecs.umich.edu if (all) { 4617639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint32_t>( 4627639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4637639Sgblack@eecs.umich.edu } else { 4647639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint32_t>( 4657639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4667639Sgblack@eecs.umich.edu } 4677639Sgblack@eecs.umich.edu break; 4687639Sgblack@eecs.umich.edu default: 4697853SMatt.Horsnell@ARM.com // Bad size 4707853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4717639Sgblack@eecs.umich.edu break; 4727639Sgblack@eecs.umich.edu } 4737639Sgblack@eecs.umich.edu break; 4747639Sgblack@eecs.umich.edu case 1: 4757639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 4767639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4777639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 4787639Sgblack@eecs.umich.edu switch (size) { 4797639Sgblack@eecs.umich.edu case 0: 4807639Sgblack@eecs.umich.edu if (all) { 4817639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4827639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint8_t>( 4837639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4847639Sgblack@eecs.umich.edu } else { 4857639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4867639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint8_t>( 4877639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4887639Sgblack@eecs.umich.edu } 4897639Sgblack@eecs.umich.edu break; 4907639Sgblack@eecs.umich.edu case 1: 4917639Sgblack@eecs.umich.edu if (all) { 4927639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4937639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint16_t>( 4947639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4957639Sgblack@eecs.umich.edu } else { 4967639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4977639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint16_t>( 4987639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4997639Sgblack@eecs.umich.edu } 5007639Sgblack@eecs.umich.edu break; 5017639Sgblack@eecs.umich.edu case 2: 5027639Sgblack@eecs.umich.edu if (all) { 5037639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5047639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint32_t>( 5057639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 5067639Sgblack@eecs.umich.edu } else { 5077639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5087639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint32_t>( 5097639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 5107639Sgblack@eecs.umich.edu } 5117639Sgblack@eecs.umich.edu break; 5127639Sgblack@eecs.umich.edu default: 5137853SMatt.Horsnell@ARM.com // Bad size 5147853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5157639Sgblack@eecs.umich.edu break; 5167639Sgblack@eecs.umich.edu } 5177639Sgblack@eecs.umich.edu } 5187639Sgblack@eecs.umich.edu break; 5197639Sgblack@eecs.umich.edu default: 5207853SMatt.Horsnell@ARM.com // Bad number of elements to unpack 5217853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5227639Sgblack@eecs.umich.edu } 5237639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 5247639Sgblack@eecs.umich.edu 5257639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 5267639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 5277639Sgblack@eecs.umich.edu assert(uopPtr); 5287639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 5297639Sgblack@eecs.umich.edu } 5307639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 5317639Sgblack@eecs.umich.edu} 5327639Sgblack@eecs.umich.edu 5337639Sgblack@eecs.umich.eduVstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 5347639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 5357639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 5367639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 5377639Sgblack@eecs.umich.edu{ 5387639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 5397639Sgblack@eecs.umich.edu assert(regs % elems == 0); 5407639Sgblack@eecs.umich.edu 5417639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 5427639Sgblack@eecs.umich.edu bool wb = (rm != 15); 5437639Sgblack@eecs.umich.edu bool interleave = (elems > 1); 5447639Sgblack@eecs.umich.edu 5457639Sgblack@eecs.umich.edu if (wb) numMicroops++; 5467639Sgblack@eecs.umich.edu if (interleave) numMicroops += (regs / elems); 5477639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 5487639Sgblack@eecs.umich.edu 5497639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 5507639Sgblack@eecs.umich.edu 5517639Sgblack@eecs.umich.edu RegIndex rMid = interleave ? NumFloatArchRegs : vd * 2; 5527639Sgblack@eecs.umich.edu 5537639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 5547639Sgblack@eecs.umich.edu if (interleave) { 5557639Sgblack@eecs.umich.edu switch (elems) { 5567639Sgblack@eecs.umich.edu case 4: 5577639Sgblack@eecs.umich.edu assert(regs == 4); 5587639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon8Uop>( 5597639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5607639Sgblack@eecs.umich.edu break; 5617639Sgblack@eecs.umich.edu case 3: 5627639Sgblack@eecs.umich.edu assert(regs == 3); 5637639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon6Uop>( 5647639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5657639Sgblack@eecs.umich.edu break; 5667639Sgblack@eecs.umich.edu case 2: 5677639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 5687639Sgblack@eecs.umich.edu if (regs == 4) { 5697639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5707639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5717639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5727639Sgblack@eecs.umich.edu size, machInst, rMid + 4, vd * 2 + 2, inc * 2); 5737639Sgblack@eecs.umich.edu } else { 5747639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5757639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5767639Sgblack@eecs.umich.edu } 5777639Sgblack@eecs.umich.edu break; 5787639Sgblack@eecs.umich.edu default: 5797853SMatt.Horsnell@ARM.com // Bad number of elements to interleave 5807853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5817639Sgblack@eecs.umich.edu } 5827639Sgblack@eecs.umich.edu } 5837639Sgblack@eecs.umich.edu switch (regs) { 5847639Sgblack@eecs.umich.edu case 4: 5857639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5867639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5877639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5887639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5897639Sgblack@eecs.umich.edu break; 5907639Sgblack@eecs.umich.edu case 3: 5917639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5927639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5937639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5947639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5957639Sgblack@eecs.umich.edu break; 5967639Sgblack@eecs.umich.edu case 2: 5977639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5987639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5997639Sgblack@eecs.umich.edu break; 6007639Sgblack@eecs.umich.edu case 1: 6017639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 6027639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 6037639Sgblack@eecs.umich.edu break; 6047639Sgblack@eecs.umich.edu default: 6057853SMatt.Horsnell@ARM.com // Unknown number of registers 6067853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6077639Sgblack@eecs.umich.edu } 6087639Sgblack@eecs.umich.edu if (wb) { 6097639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 6107639Sgblack@eecs.umich.edu microOps[uopIdx++] = 6117646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 6127639Sgblack@eecs.umich.edu } else { 6137639Sgblack@eecs.umich.edu microOps[uopIdx++] = 6147639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 6157639Sgblack@eecs.umich.edu } 6167639Sgblack@eecs.umich.edu } 6177639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 6187639Sgblack@eecs.umich.edu 6197639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 6207639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 6217639Sgblack@eecs.umich.edu assert(uopPtr); 6227639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 6237639Sgblack@eecs.umich.edu } 6247639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 6257639Sgblack@eecs.umich.edu} 6267639Sgblack@eecs.umich.edu 6277639Sgblack@eecs.umich.eduVstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, 6287639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 6297639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 6307639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 6317639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 6327639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 6337639Sgblack@eecs.umich.edu{ 6347639Sgblack@eecs.umich.edu assert(!all); 6357639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 6367639Sgblack@eecs.umich.edu assert(regs % elems == 0); 6377639Sgblack@eecs.umich.edu 6387639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 6397639Sgblack@eecs.umich.edu unsigned storeSize = eBytes * elems; 6407639Sgblack@eecs.umich.edu unsigned storeRegs M5_VAR_USED = (storeSize + sizeof(FloatRegBits) - 1) / 6417639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 6427639Sgblack@eecs.umich.edu 6437639Sgblack@eecs.umich.edu assert(storeRegs > 0 && storeRegs <= 4); 6447639Sgblack@eecs.umich.edu 6457639Sgblack@eecs.umich.edu numMicroops = 1; 6467639Sgblack@eecs.umich.edu bool wb = (rm != 15); 6477639Sgblack@eecs.umich.edu 6487639Sgblack@eecs.umich.edu if (wb) numMicroops++; 6497639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 6507639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 6517639Sgblack@eecs.umich.edu 6527639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 6537639Sgblack@eecs.umich.edu 6547639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 6557639Sgblack@eecs.umich.edu switch (elems) { 6567639Sgblack@eecs.umich.edu case 4: 6577639Sgblack@eecs.umich.edu assert(regs == 4); 6587639Sgblack@eecs.umich.edu switch (size) { 6597639Sgblack@eecs.umich.edu case 0: 6607639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint8_t>( 6617639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6627639Sgblack@eecs.umich.edu break; 6637639Sgblack@eecs.umich.edu case 1: 6647639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint16_t>( 6657639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6667639Sgblack@eecs.umich.edu break; 6677639Sgblack@eecs.umich.edu case 2: 6687639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to4Uop<uint32_t>( 6697639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6707639Sgblack@eecs.umich.edu break; 6717639Sgblack@eecs.umich.edu default: 6727853SMatt.Horsnell@ARM.com // Bad size 6737853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6747639Sgblack@eecs.umich.edu break; 6757639Sgblack@eecs.umich.edu } 6767639Sgblack@eecs.umich.edu break; 6777639Sgblack@eecs.umich.edu case 3: 6787639Sgblack@eecs.umich.edu assert(regs == 3); 6797639Sgblack@eecs.umich.edu switch (size) { 6807639Sgblack@eecs.umich.edu case 0: 6817639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint8_t>( 6827639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6837639Sgblack@eecs.umich.edu break; 6847639Sgblack@eecs.umich.edu case 1: 6857639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint16_t>( 6867639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6877639Sgblack@eecs.umich.edu break; 6887639Sgblack@eecs.umich.edu case 2: 6897639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to4Uop<uint32_t>( 6907639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6917639Sgblack@eecs.umich.edu break; 6927639Sgblack@eecs.umich.edu default: 6937853SMatt.Horsnell@ARM.com // Bad size 6947853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6957639Sgblack@eecs.umich.edu break; 6967639Sgblack@eecs.umich.edu } 6977639Sgblack@eecs.umich.edu break; 6987639Sgblack@eecs.umich.edu case 2: 6997639Sgblack@eecs.umich.edu assert(regs == 2); 7007639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 7017639Sgblack@eecs.umich.edu switch (size) { 7027639Sgblack@eecs.umich.edu case 0: 7037639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint8_t>( 7047639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 7057639Sgblack@eecs.umich.edu break; 7067639Sgblack@eecs.umich.edu case 1: 7077639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint16_t>( 7087639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 7097639Sgblack@eecs.umich.edu break; 7107639Sgblack@eecs.umich.edu case 2: 7117639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint32_t>( 7127639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 7137639Sgblack@eecs.umich.edu break; 7147639Sgblack@eecs.umich.edu default: 7157853SMatt.Horsnell@ARM.com // Bad size 7167853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7177639Sgblack@eecs.umich.edu break; 7187639Sgblack@eecs.umich.edu } 7197639Sgblack@eecs.umich.edu break; 7207639Sgblack@eecs.umich.edu case 1: 7217639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 7227639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 7237639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 7247639Sgblack@eecs.umich.edu switch (size) { 7257639Sgblack@eecs.umich.edu case 0: 7267639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint8_t>( 7277639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7287639Sgblack@eecs.umich.edu break; 7297639Sgblack@eecs.umich.edu case 1: 7307639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint16_t>( 7317639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7327639Sgblack@eecs.umich.edu break; 7337639Sgblack@eecs.umich.edu case 2: 7347639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint32_t>( 7357639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7367639Sgblack@eecs.umich.edu break; 7377639Sgblack@eecs.umich.edu default: 7387853SMatt.Horsnell@ARM.com // Bad size 7397853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7407639Sgblack@eecs.umich.edu break; 7417639Sgblack@eecs.umich.edu } 7427639Sgblack@eecs.umich.edu } 7437639Sgblack@eecs.umich.edu break; 7447639Sgblack@eecs.umich.edu default: 7457853SMatt.Horsnell@ARM.com // Bad number of elements to unpack 7467853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7477639Sgblack@eecs.umich.edu } 7487639Sgblack@eecs.umich.edu switch (storeSize) { 7497639Sgblack@eecs.umich.edu case 1: 7507639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon1Uop<uint8_t>( 7517639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7527639Sgblack@eecs.umich.edu break; 7537639Sgblack@eecs.umich.edu case 2: 7547639Sgblack@eecs.umich.edu if (eBytes == 2) { 7557639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint16_t>( 7567639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7577639Sgblack@eecs.umich.edu } else { 7587639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint8_t>( 7597639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7607639Sgblack@eecs.umich.edu } 7617639Sgblack@eecs.umich.edu break; 7627639Sgblack@eecs.umich.edu case 3: 7637639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon3Uop<uint8_t>( 7647639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7657639Sgblack@eecs.umich.edu break; 7667639Sgblack@eecs.umich.edu case 4: 7677639Sgblack@eecs.umich.edu switch (eBytes) { 7687639Sgblack@eecs.umich.edu case 1: 7697639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint8_t>( 7707639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7717639Sgblack@eecs.umich.edu break; 7727639Sgblack@eecs.umich.edu case 2: 7737639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint16_t>( 7747639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7757639Sgblack@eecs.umich.edu break; 7767639Sgblack@eecs.umich.edu case 4: 7777639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint32_t>( 7787639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7797639Sgblack@eecs.umich.edu break; 7807639Sgblack@eecs.umich.edu } 7817639Sgblack@eecs.umich.edu break; 7827639Sgblack@eecs.umich.edu case 6: 7837639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon6Uop<uint16_t>( 7847639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7857639Sgblack@eecs.umich.edu break; 7867639Sgblack@eecs.umich.edu case 8: 7877639Sgblack@eecs.umich.edu switch (eBytes) { 7887639Sgblack@eecs.umich.edu case 2: 7897639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint16_t>( 7907639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7917639Sgblack@eecs.umich.edu break; 7927639Sgblack@eecs.umich.edu case 4: 7937639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint32_t>( 7947639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7957639Sgblack@eecs.umich.edu break; 7967639Sgblack@eecs.umich.edu } 7977639Sgblack@eecs.umich.edu break; 7987639Sgblack@eecs.umich.edu case 12: 7997639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon12Uop<uint32_t>( 8007639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 8017639Sgblack@eecs.umich.edu break; 8027639Sgblack@eecs.umich.edu case 16: 8037639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon16Uop<uint32_t>( 8047639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 8057639Sgblack@eecs.umich.edu break; 8067639Sgblack@eecs.umich.edu default: 8077853SMatt.Horsnell@ARM.com // Bad store size 8087853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 8097639Sgblack@eecs.umich.edu } 8107639Sgblack@eecs.umich.edu if (wb) { 8117639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 8127639Sgblack@eecs.umich.edu microOps[uopIdx++] = 8137646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 8147639Sgblack@eecs.umich.edu } else { 8157639Sgblack@eecs.umich.edu microOps[uopIdx++] = 8167639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, storeSize); 8177639Sgblack@eecs.umich.edu } 8187639Sgblack@eecs.umich.edu } 8197639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 8207639Sgblack@eecs.umich.edu 8217639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 8227639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 8237639Sgblack@eecs.umich.edu assert(uopPtr); 8247639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 8257639Sgblack@eecs.umich.edu } 8267639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 8277639Sgblack@eecs.umich.edu} 8287639Sgblack@eecs.umich.edu 8297175Sgblack@eecs.umich.eduMacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst, 8307175Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 8317175Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, 8327175Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t offset) : 8337175Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 8347175Sgblack@eecs.umich.edu{ 8357175Sgblack@eecs.umich.edu int i = 0; 8367175Sgblack@eecs.umich.edu 8377175Sgblack@eecs.umich.edu // The lowest order bit selects fldmx (set) or fldmd (clear). These seem 8387175Sgblack@eecs.umich.edu // to be functionally identical except that fldmx is deprecated. For now 8397175Sgblack@eecs.umich.edu // we'll assume they're otherwise interchangable. 8407175Sgblack@eecs.umich.edu int count = (single ? offset : (offset / 2)); 8417175Sgblack@eecs.umich.edu if (count == 0 || count > NumFloatArchRegs) 8427175Sgblack@eecs.umich.edu warn_once("Bad offset field for VFP load/store multiple.\n"); 8437175Sgblack@eecs.umich.edu if (count == 0) { 8447175Sgblack@eecs.umich.edu // Force there to be at least one microop so the macroop makes sense. 8457175Sgblack@eecs.umich.edu writeback = true; 8467175Sgblack@eecs.umich.edu } 8477175Sgblack@eecs.umich.edu if (count > NumFloatArchRegs) 8487175Sgblack@eecs.umich.edu count = NumFloatArchRegs; 8497175Sgblack@eecs.umich.edu 8507342Sgblack@eecs.umich.edu numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0); 8517342Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 8527342Sgblack@eecs.umich.edu 8537395Sgblack@eecs.umich.edu int64_t addr = 0; 8547175Sgblack@eecs.umich.edu 8557342Sgblack@eecs.umich.edu if (!up) 8567342Sgblack@eecs.umich.edu addr = 4 * offset; 8577175Sgblack@eecs.umich.edu 8587342Sgblack@eecs.umich.edu bool tempUp = up; 8597175Sgblack@eecs.umich.edu for (int j = 0; j < count; j++) { 8607175Sgblack@eecs.umich.edu if (load) { 8617639Sgblack@eecs.umich.edu if (single) { 8627639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, 8637639Sgblack@eecs.umich.edu tempUp, addr); 8647639Sgblack@eecs.umich.edu } else { 8657639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDBFpUop(machInst, vd++, rn, 8667639Sgblack@eecs.umich.edu tempUp, addr); 8677639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDTFpUop(machInst, vd++, rn, tempUp, 8687639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8697639Sgblack@eecs.umich.edu } 8707175Sgblack@eecs.umich.edu } else { 8717639Sgblack@eecs.umich.edu if (single) { 8727639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, 8737639Sgblack@eecs.umich.edu tempUp, addr); 8747639Sgblack@eecs.umich.edu } else { 8757639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDBFpUop(machInst, vd++, rn, 8767639Sgblack@eecs.umich.edu tempUp, addr); 8777639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDTFpUop(machInst, vd++, rn, tempUp, 8787639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8797639Sgblack@eecs.umich.edu } 8807175Sgblack@eecs.umich.edu } 8817342Sgblack@eecs.umich.edu if (!tempUp) { 8827342Sgblack@eecs.umich.edu addr -= (single ? 4 : 8); 8837342Sgblack@eecs.umich.edu // The microops don't handle negative displacement, so turn if we 8847342Sgblack@eecs.umich.edu // hit zero, flip polarity and start adding. 8857395Sgblack@eecs.umich.edu if (addr <= 0) { 8867342Sgblack@eecs.umich.edu tempUp = true; 8877395Sgblack@eecs.umich.edu addr = -addr; 8887342Sgblack@eecs.umich.edu } 8897342Sgblack@eecs.umich.edu } else { 8907342Sgblack@eecs.umich.edu addr += (single ? 4 : 8); 8917342Sgblack@eecs.umich.edu } 8927175Sgblack@eecs.umich.edu } 8937175Sgblack@eecs.umich.edu 8947175Sgblack@eecs.umich.edu if (writeback) { 8957175Sgblack@eecs.umich.edu if (up) { 8967175Sgblack@eecs.umich.edu microOps[i++] = 8977175Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, 4 * offset); 8987175Sgblack@eecs.umich.edu } else { 8997175Sgblack@eecs.umich.edu microOps[i++] = 9007175Sgblack@eecs.umich.edu new MicroSubiUop(machInst, rn, rn, 4 * offset); 9017175Sgblack@eecs.umich.edu } 9027175Sgblack@eecs.umich.edu } 9037175Sgblack@eecs.umich.edu 9047342Sgblack@eecs.umich.edu assert(numMicroops == i); 9057175Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 9067343Sgblack@eecs.umich.edu 9077343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 9087343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 9097343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 9107343Sgblack@eecs.umich.edu assert(uopPtr); 9117343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 9127343Sgblack@eecs.umich.edu } 9137170Sgblack@eecs.umich.edu} 9147175Sgblack@eecs.umich.edu 9157615Sminkyu.jeong@arm.comstd::string 9167639Sgblack@eecs.umich.eduMicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9177639Sgblack@eecs.umich.edu{ 9187639Sgblack@eecs.umich.edu std::stringstream ss; 9197639Sgblack@eecs.umich.edu printMnemonic(ss); 9207639Sgblack@eecs.umich.edu printReg(ss, ura); 9217639Sgblack@eecs.umich.edu ss << ", "; 9227639Sgblack@eecs.umich.edu printReg(ss, urb); 9237639Sgblack@eecs.umich.edu ss << ", "; 9247639Sgblack@eecs.umich.edu ccprintf(ss, "#%d", imm); 9257639Sgblack@eecs.umich.edu return ss.str(); 9267639Sgblack@eecs.umich.edu} 9277639Sgblack@eecs.umich.edu 9287639Sgblack@eecs.umich.edustd::string 9298140SMatt.Horsnell@arm.comMicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9308140SMatt.Horsnell@arm.com{ 9318140SMatt.Horsnell@arm.com std::stringstream ss; 9328140SMatt.Horsnell@arm.com printMnemonic(ss); 9338140SMatt.Horsnell@arm.com ss << "[PC,CPSR]"; 9348140SMatt.Horsnell@arm.com return ss.str(); 9358140SMatt.Horsnell@arm.com} 9368140SMatt.Horsnell@arm.com 9378140SMatt.Horsnell@arm.comstd::string 9387646Sgene.wu@arm.comMicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9397646Sgene.wu@arm.com{ 9407646Sgene.wu@arm.com std::stringstream ss; 9417646Sgene.wu@arm.com printMnemonic(ss); 9427646Sgene.wu@arm.com printReg(ss, ura); 9437646Sgene.wu@arm.com ss << ", "; 9447646Sgene.wu@arm.com printReg(ss, urb); 9457646Sgene.wu@arm.com return ss.str(); 9467646Sgene.wu@arm.com} 9477646Sgene.wu@arm.com 9487646Sgene.wu@arm.comstd::string 9497615Sminkyu.jeong@arm.comMicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9507615Sminkyu.jeong@arm.com{ 9517615Sminkyu.jeong@arm.com std::stringstream ss; 9527615Sminkyu.jeong@arm.com printMnemonic(ss); 9537615Sminkyu.jeong@arm.com printReg(ss, ura); 9547615Sminkyu.jeong@arm.com ss << ", "; 9557615Sminkyu.jeong@arm.com printReg(ss, urb); 9567615Sminkyu.jeong@arm.com ss << ", "; 9577639Sgblack@eecs.umich.edu printReg(ss, urc); 9587615Sminkyu.jeong@arm.com return ss.str(); 9597175Sgblack@eecs.umich.edu} 9607615Sminkyu.jeong@arm.com 9617615Sminkyu.jeong@arm.comstd::string 9627615Sminkyu.jeong@arm.comMicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9637615Sminkyu.jeong@arm.com{ 9647615Sminkyu.jeong@arm.com std::stringstream ss; 9657615Sminkyu.jeong@arm.com printMnemonic(ss); 9667615Sminkyu.jeong@arm.com printReg(ss, ura); 9677615Sminkyu.jeong@arm.com ss << ", ["; 9687615Sminkyu.jeong@arm.com printReg(ss, urb); 9697615Sminkyu.jeong@arm.com ss << ", "; 9707615Sminkyu.jeong@arm.com ccprintf(ss, "#%d", imm); 9717615Sminkyu.jeong@arm.com ss << "]"; 9727615Sminkyu.jeong@arm.com return ss.str(); 9737615Sminkyu.jeong@arm.com} 9747615Sminkyu.jeong@arm.com 9757615Sminkyu.jeong@arm.com} 976