branch64.hh revision 10037
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2011-2013 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Gabe Black 3810037SARM gem5 Developers */ 3910037SARM gem5 Developers#ifndef __ARCH_ARM_INSTS_BRANCH64_HH__ 4010037SARM gem5 Developers#define __ARCH_ARM_INSTS_BRANCH64_HH__ 4110037SARM gem5 Developers 4210037SARM gem5 Developers#include "arch/arm/insts/static_inst.hh" 4310037SARM gem5 Developers 4410037SARM gem5 Developersnamespace ArmISA 4510037SARM gem5 Developers{ 4610037SARM gem5 Developers// Branch to a target computed with an immediate 4710037SARM gem5 Developersclass BranchImm64 : public ArmStaticInst 4810037SARM gem5 Developers{ 4910037SARM gem5 Developers protected: 5010037SARM gem5 Developers int64_t imm; 5110037SARM gem5 Developers 5210037SARM gem5 Developers public: 5310037SARM gem5 Developers BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 5410037SARM gem5 Developers int64_t _imm) : 5510037SARM gem5 Developers ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) 5610037SARM gem5 Developers {} 5710037SARM gem5 Developers 5810037SARM gem5 Developers ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 5910037SARM gem5 Developers 6010037SARM gem5 Developers /// Explicitly import the otherwise hidden branchTarget 6110037SARM gem5 Developers using StaticInst::branchTarget; 6210037SARM gem5 Developers 6310037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 6410037SARM gem5 Developers}; 6510037SARM gem5 Developers 6610037SARM gem5 Developers// Conditionally Branch to a target computed with an immediate 6710037SARM gem5 Developersclass BranchImmCond64 : public BranchImm64 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers protected: 7010037SARM gem5 Developers ConditionCode condCode; 7110037SARM gem5 Developers 7210037SARM gem5 Developers public: 7310037SARM gem5 Developers BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 7410037SARM gem5 Developers int64_t _imm, ConditionCode _condCode) : 7510037SARM gem5 Developers BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode) 7610037SARM gem5 Developers {} 7710037SARM gem5 Developers 7810037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 7910037SARM gem5 Developers}; 8010037SARM gem5 Developers 8110037SARM gem5 Developers// Branch to a target computed with a register 8210037SARM gem5 Developersclass BranchReg64 : public ArmStaticInst 8310037SARM gem5 Developers{ 8410037SARM gem5 Developers protected: 8510037SARM gem5 Developers IntRegIndex op1; 8610037SARM gem5 Developers 8710037SARM gem5 Developers public: 8810037SARM gem5 Developers BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 8910037SARM gem5 Developers IntRegIndex _op1) : 9010037SARM gem5 Developers ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) 9110037SARM gem5 Developers {} 9210037SARM gem5 Developers 9310037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 9410037SARM gem5 Developers}; 9510037SARM gem5 Developers 9610037SARM gem5 Developers// Ret instruction 9710037SARM gem5 Developersclass BranchRet64 : public BranchReg64 9810037SARM gem5 Developers{ 9910037SARM gem5 Developers public: 10010037SARM gem5 Developers BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 10110037SARM gem5 Developers IntRegIndex _op1) : 10210037SARM gem5 Developers BranchReg64(mnem, _machInst, __opClass, _op1) 10310037SARM gem5 Developers {} 10410037SARM gem5 Developers 10510037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 10610037SARM gem5 Developers}; 10710037SARM gem5 Developers 10810037SARM gem5 Developers// Eret instruction 10910037SARM gem5 Developersclass BranchEret64 : public ArmStaticInst 11010037SARM gem5 Developers{ 11110037SARM gem5 Developers public: 11210037SARM gem5 Developers BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 11310037SARM gem5 Developers ArmStaticInst(mnem, _machInst, __opClass) 11410037SARM gem5 Developers {} 11510037SARM gem5 Developers 11610037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 11710037SARM gem5 Developers}; 11810037SARM gem5 Developers 11910037SARM gem5 Developers// Branch to a target computed with an immediate and a register 12010037SARM gem5 Developersclass BranchImmReg64 : public ArmStaticInst 12110037SARM gem5 Developers{ 12210037SARM gem5 Developers protected: 12310037SARM gem5 Developers int64_t imm; 12410037SARM gem5 Developers IntRegIndex op1; 12510037SARM gem5 Developers 12610037SARM gem5 Developers public: 12710037SARM gem5 Developers BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 12810037SARM gem5 Developers int64_t _imm, IntRegIndex _op1) : 12910037SARM gem5 Developers ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1) 13010037SARM gem5 Developers {} 13110037SARM gem5 Developers 13210037SARM gem5 Developers ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 13310037SARM gem5 Developers 13410037SARM gem5 Developers /// Explicitly import the otherwise hidden branchTarget 13510037SARM gem5 Developers using StaticInst::branchTarget; 13610037SARM gem5 Developers 13710037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 13810037SARM gem5 Developers}; 13910037SARM gem5 Developers 14010037SARM gem5 Developers// Branch to a target computed with two immediates 14110037SARM gem5 Developersclass BranchImmImmReg64 : public ArmStaticInst 14210037SARM gem5 Developers{ 14310037SARM gem5 Developers protected: 14410037SARM gem5 Developers int64_t imm1; 14510037SARM gem5 Developers int64_t imm2; 14610037SARM gem5 Developers IntRegIndex op1; 14710037SARM gem5 Developers 14810037SARM gem5 Developers public: 14910037SARM gem5 Developers BranchImmImmReg64(const char *mnem, ExtMachInst _machInst, 15010037SARM gem5 Developers OpClass __opClass, int64_t _imm1, int64_t _imm2, 15110037SARM gem5 Developers IntRegIndex _op1) : 15210037SARM gem5 Developers ArmStaticInst(mnem, _machInst, __opClass), 15310037SARM gem5 Developers imm1(_imm1), imm2(_imm2), op1(_op1) 15410037SARM gem5 Developers {} 15510037SARM gem5 Developers 15610037SARM gem5 Developers ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 15710037SARM gem5 Developers 15810037SARM gem5 Developers /// Explicitly import the otherwise hidden branchTarget 15910037SARM gem5 Developers using StaticInst::branchTarget; 16010037SARM gem5 Developers 16110037SARM gem5 Developers std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 16210037SARM gem5 Developers}; 16310037SARM gem5 Developers 16410037SARM gem5 Developers} 16510037SARM gem5 Developers 16610037SARM gem5 Developers#endif //__ARCH_ARM_INSTS_BRANCH_HH__ 167