branch64.cc revision 12104:edd63f9c6184 
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/branch64.hh"
41
42namespace ArmISA
43{
44
45ArmISA::PCState
46BranchImm64::branchTarget(const ArmISA::PCState &branchPC) const
47{
48    ArmISA::PCState pcs = branchPC;
49    pcs.instNPC(pcs.pc() + imm);
50    pcs.advance();
51    return pcs;
52}
53
54ArmISA::PCState
55BranchImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
56{
57    ArmISA::PCState pcs = branchPC;
58    pcs.instNPC(pcs.pc() + imm);
59    pcs.advance();
60    return pcs;
61}
62
63ArmISA::PCState
64BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
65{
66    ArmISA::PCState pcs = branchPC;
67    pcs.instNPC(pcs.pc() + imm2);
68    pcs.advance();
69    return pcs;
70}
71
72std::string
73BranchImmCond64::generateDisassembly(
74        Addr pc, const SymbolTable *symtab) const
75{
76    std::stringstream ss;
77    printMnemonic(ss, "", false, true, condCode);
78    printTarget(ss, pc + imm, symtab);
79    return ss.str();
80}
81
82std::string
83BranchImm64::generateDisassembly(
84        Addr pc, const SymbolTable *symtab) const
85{
86    std::stringstream ss;
87    printMnemonic(ss, "", false);
88    printTarget(ss, pc + imm, symtab);
89    return ss.str();
90}
91
92std::string
93BranchReg64::generateDisassembly(
94        Addr pc, const SymbolTable *symtab) const
95{
96    std::stringstream ss;
97    printMnemonic(ss, "", false);
98    printIntReg(ss, op1);
99    return ss.str();
100}
101
102std::string
103BranchRet64::generateDisassembly(
104        Addr pc, const SymbolTable *symtab) const
105{
106    std::stringstream ss;
107    printMnemonic(ss, "", false);
108    if (op1 != INTREG_X30)
109        printIntReg(ss, op1);
110    return ss.str();
111}
112
113std::string
114BranchEret64::generateDisassembly(
115        Addr pc, const SymbolTable *symtab) const
116{
117    std::stringstream ss;
118    printMnemonic(ss, "", false);
119    return ss.str();
120}
121
122std::string
123BranchImmReg64::generateDisassembly(
124        Addr pc, const SymbolTable *symtab) const
125{
126    std::stringstream ss;
127    printMnemonic(ss, "", false);
128    printIntReg(ss, op1);
129    ccprintf(ss, ", ");
130    printTarget(ss, pc + imm, symtab);
131    return ss.str();
132}
133
134std::string
135BranchImmImmReg64::generateDisassembly(
136        Addr pc, const SymbolTable *symtab) const
137{
138    std::stringstream ss;
139    printMnemonic(ss, "", false);
140    printIntReg(ss, op1);
141    ccprintf(ss, ", #%#x, ", imm1);
142    printTarget(ss, pc + imm2, symtab);
143    return ss.str();
144}
145
146} // namespace ArmISA
147