branch.hh revision 7153:6ce0bf0ddaf3
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_INSTS_BRANCH_HH__ 43#define __ARCH_ARM_INSTS_BRANCH_HH__ 44 45#include "arch/arm/insts/pred_inst.hh" 46 47namespace ArmISA 48{ 49// Branch to a target computed with an immediate 50class BranchImm : public PredOp 51{ 52 protected: 53 int32_t imm; 54 55 public: 56 BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 57 int32_t _imm) : 58 PredOp(mnem, _machInst, __opClass), imm(_imm) 59 {} 60}; 61 62// Conditionally Branch to a target computed with an immediate 63class BranchImmCond : public BranchImm 64{ 65 protected: 66 // This will mask the condition code stored for PredOp. Ideally these two 67 // class would cooperate, but they're not set up to do that at the moment. 68 ConditionCode condCode; 69 70 public: 71 BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 72 int32_t _imm, ConditionCode _condCode) : 73 BranchImm(mnem, _machInst, __opClass, _imm), condCode(_condCode) 74 {} 75}; 76 77// Branch to a target computed with a register 78class BranchReg : public PredOp 79{ 80 protected: 81 IntRegIndex op1; 82 83 public: 84 BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 85 IntRegIndex _op1) : 86 PredOp(mnem, _machInst, __opClass), op1(_op1) 87 {} 88}; 89 90// Conditionally Branch to a target computed with a register 91class BranchRegCond : public BranchReg 92{ 93 protected: 94 // This will mask the condition code stored for PredOp. Ideally these two 95 // class would cooperate, but they're not set up to do that at the moment. 96 ConditionCode condCode; 97 98 public: 99 BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 100 IntRegIndex _op1, ConditionCode _condCode) : 101 BranchReg(mnem, _machInst, __opClass, _op1), condCode(_condCode) 102 {} 103}; 104 105// Branch to a target computed with two registers 106class BranchRegReg : public PredOp 107{ 108 protected: 109 IntRegIndex op1; 110 IntRegIndex op2; 111 112 public: 113 BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 114 IntRegIndex _op1, IntRegIndex _op2) : 115 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) 116 {} 117}; 118 119// Branch to a target computed with an immediate and a register 120class BranchImmReg : public PredOp 121{ 122 protected: 123 int32_t imm; 124 IntRegIndex op1; 125 126 public: 127 BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 128 int32_t _imm, IntRegIndex _op1) : 129 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1) 130 {} 131}; 132 133} 134 135#endif //__ARCH_ARM_INSTS_BRANCH_HH__ 136