branch.hh revision 8909
111482Sandreas.sandberg@arm.com/* 211482Sandreas.sandberg@arm.com * Copyright (c) 2010 ARM Limited 311482Sandreas.sandberg@arm.com * All rights reserved 411482Sandreas.sandberg@arm.com * 511482Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 611482Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 711482Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 811482Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 911482Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1011482Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1111482Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1211482Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1311482Sandreas.sandberg@arm.com * 1411482Sandreas.sandberg@arm.com * Copyright (c) 2007-2008 The Florida State University 1511482Sandreas.sandberg@arm.com * All rights reserved. 1611482Sandreas.sandberg@arm.com * 1711482Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1811482Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1911482Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2011482Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2111482Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2211482Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2311482Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2411482Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2511482Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2611482Sandreas.sandberg@arm.com * this software without specific prior written permission. 2711482Sandreas.sandberg@arm.com * 2811482Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911482Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011482Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111482Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211482Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311482Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411482Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511482Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611482Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711482Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811482Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911482Sandreas.sandberg@arm.com * 4011482Sandreas.sandberg@arm.com * Authors: Stephen Hines 4111482Sandreas.sandberg@arm.com */ 4211482Sandreas.sandberg@arm.com#ifndef __ARCH_ARM_INSTS_BRANCH_HH__ 4311482Sandreas.sandberg@arm.com#define __ARCH_ARM_INSTS_BRANCH_HH__ 4411482Sandreas.sandberg@arm.com 4511482Sandreas.sandberg@arm.com#include "arch/arm/insts/pred_inst.hh" 4611482Sandreas.sandberg@arm.com 4711482Sandreas.sandberg@arm.comnamespace ArmISA 4811482Sandreas.sandberg@arm.com{ 4911482Sandreas.sandberg@arm.com// Branch to a target computed with an immediate 5011482Sandreas.sandberg@arm.comclass BranchImm : public PredOp 5111482Sandreas.sandberg@arm.com{ 5211482Sandreas.sandberg@arm.com protected: 5311482Sandreas.sandberg@arm.com int32_t imm; 5411482Sandreas.sandberg@arm.com 5511482Sandreas.sandberg@arm.com public: 5611482Sandreas.sandberg@arm.com BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 5711482Sandreas.sandberg@arm.com int32_t _imm) : 5811482Sandreas.sandberg@arm.com PredOp(mnem, _machInst, __opClass), imm(_imm) 5911482Sandreas.sandberg@arm.com {} 6011482Sandreas.sandberg@arm.com 6111482Sandreas.sandberg@arm.com}; 6211482Sandreas.sandberg@arm.com 6311482Sandreas.sandberg@arm.com// Conditionally Branch to a target computed with an immediate 6411482Sandreas.sandberg@arm.comclass BranchImmCond : public BranchImm 6511482Sandreas.sandberg@arm.com{ 6611482Sandreas.sandberg@arm.com public: 6711482Sandreas.sandberg@arm.com BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 6811482Sandreas.sandberg@arm.com int32_t _imm, ConditionCode _condCode) : 6911482Sandreas.sandberg@arm.com BranchImm(mnem, _machInst, __opClass, _imm) 7011482Sandreas.sandberg@arm.com { 7111482Sandreas.sandberg@arm.com // Only update if this isn't part of an IT block 7211482Sandreas.sandberg@arm.com if (!machInst.itstateMask) 7311482Sandreas.sandberg@arm.com condCode = _condCode; 7411482Sandreas.sandberg@arm.com } 7511482Sandreas.sandberg@arm.com}; 7611482Sandreas.sandberg@arm.com 7711482Sandreas.sandberg@arm.com// Branch to a target computed with a register 7811482Sandreas.sandberg@arm.comclass BranchReg : public PredOp 7911482Sandreas.sandberg@arm.com{ 8011482Sandreas.sandberg@arm.com protected: 8111482Sandreas.sandberg@arm.com IntRegIndex op1; 8211482Sandreas.sandberg@arm.com 8311482Sandreas.sandberg@arm.com public: 8411482Sandreas.sandberg@arm.com BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 8511482Sandreas.sandberg@arm.com IntRegIndex _op1) : 8611482Sandreas.sandberg@arm.com PredOp(mnem, _machInst, __opClass), op1(_op1) 8711482Sandreas.sandberg@arm.com {} 8811482Sandreas.sandberg@arm.com}; 8911482Sandreas.sandberg@arm.com 9011482Sandreas.sandberg@arm.com// Conditionally Branch to a target computed with a register 9111482Sandreas.sandberg@arm.comclass BranchRegCond : public BranchReg 9211482Sandreas.sandberg@arm.com{ 9311482Sandreas.sandberg@arm.com public: 9411482Sandreas.sandberg@arm.com BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 9511482Sandreas.sandberg@arm.com IntRegIndex _op1, ConditionCode _condCode) : 9611482Sandreas.sandberg@arm.com BranchReg(mnem, _machInst, __opClass, _op1) 9711482Sandreas.sandberg@arm.com { 9811482Sandreas.sandberg@arm.com // Only update if this isn't part of an IT block 9911482Sandreas.sandberg@arm.com if (!machInst.itstateMask) 10011482Sandreas.sandberg@arm.com condCode = _condCode; 10111482Sandreas.sandberg@arm.com } 10211482Sandreas.sandberg@arm.com}; 10311482Sandreas.sandberg@arm.com 10411482Sandreas.sandberg@arm.com// Branch to a target computed with two registers 10511482Sandreas.sandberg@arm.comclass BranchRegReg : public PredOp 10611482Sandreas.sandberg@arm.com{ 10711482Sandreas.sandberg@arm.com protected: 10811542Sandreas.sandberg@arm.com IntRegIndex op1; 10911482Sandreas.sandberg@arm.com IntRegIndex op2; 11011542Sandreas.sandberg@arm.com 11111542Sandreas.sandberg@arm.com public: 11211542Sandreas.sandberg@arm.com BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 11311482Sandreas.sandberg@arm.com IntRegIndex _op1, IntRegIndex _op2) : 11411482Sandreas.sandberg@arm.com PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) 11511542Sandreas.sandberg@arm.com {} 11611542Sandreas.sandberg@arm.com}; 11711542Sandreas.sandberg@arm.com 11811542Sandreas.sandberg@arm.com// Branch to a target computed with an immediate and a register 11911542Sandreas.sandberg@arm.comclass BranchImmReg : public PredOp 12011542Sandreas.sandberg@arm.com{ 12111542Sandreas.sandberg@arm.com protected: 12211542Sandreas.sandberg@arm.com int32_t imm; 12311542Sandreas.sandberg@arm.com IntRegIndex op1; 12411542Sandreas.sandberg@arm.com 12511542Sandreas.sandberg@arm.com public: 12611542Sandreas.sandberg@arm.com BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 12711542Sandreas.sandberg@arm.com int32_t _imm, IntRegIndex _op1) : 12811542Sandreas.sandberg@arm.com PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1) 12911542Sandreas.sandberg@arm.com {} 13011542Sandreas.sandberg@arm.com}; 13111482Sandreas.sandberg@arm.com 13211482Sandreas.sandberg@arm.com} 13311542Sandreas.sandberg@arm.com 13411482Sandreas.sandberg@arm.com#endif //__ARCH_ARM_INSTS_BRANCH_HH__ 13511512SCurtis.Dunham@arm.com