branch.hh revision 7099
16253Sgblack@eecs.umich.edu/* Copyright (c) 2007-2008 The Florida State University 26253Sgblack@eecs.umich.edu * All rights reserved. 36253Sgblack@eecs.umich.edu * 46253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 56253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 66253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 76253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 86253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 96253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 106253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 116253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 126253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 136253Sgblack@eecs.umich.edu * this software without specific prior written permission. 146253Sgblack@eecs.umich.edu * 156253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266253Sgblack@eecs.umich.edu * 276253Sgblack@eecs.umich.edu * Authors: Stephen Hines 286253Sgblack@eecs.umich.edu */ 296253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_BRANCH_HH__ 306253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_BRANCH_HH__ 316253Sgblack@eecs.umich.edu 326253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 336253Sgblack@eecs.umich.edu 346253Sgblack@eecs.umich.edunamespace ArmISA 356253Sgblack@eecs.umich.edu{ 366253Sgblack@eecs.umich.edu/** 376253Sgblack@eecs.umich.edu * Base class for instructions whose disassembly is not purely a 386253Sgblack@eecs.umich.edu * function of the machine instruction (i.e., it depends on the 396253Sgblack@eecs.umich.edu * PC). This class overrides the disassemble() method to check 406253Sgblack@eecs.umich.edu * the PC and symbol table values before re-using a cached 416253Sgblack@eecs.umich.edu * disassembly string. This is necessary for branches and jumps, 426253Sgblack@eecs.umich.edu * where the disassembly string includes the target address (which 436253Sgblack@eecs.umich.edu * may depend on the PC and/or symbol table). 446253Sgblack@eecs.umich.edu */ 456253Sgblack@eecs.umich.educlass PCDependentDisassembly : public PredOp 466253Sgblack@eecs.umich.edu{ 476253Sgblack@eecs.umich.edu protected: 486253Sgblack@eecs.umich.edu /// Cached program counter from last disassembly 496253Sgblack@eecs.umich.edu mutable Addr cachedPC; 506253Sgblack@eecs.umich.edu 516253Sgblack@eecs.umich.edu /// Cached symbol table pointer from last disassembly 526253Sgblack@eecs.umich.edu mutable const SymbolTable *cachedSymtab; 536253Sgblack@eecs.umich.edu 546253Sgblack@eecs.umich.edu /// Constructor 557099Sgblack@eecs.umich.edu PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, 566253Sgblack@eecs.umich.edu OpClass __opClass) 576253Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 586253Sgblack@eecs.umich.edu cachedPC(0), cachedSymtab(0) 596253Sgblack@eecs.umich.edu { 606253Sgblack@eecs.umich.edu } 616253Sgblack@eecs.umich.edu 626253Sgblack@eecs.umich.edu const std::string & 636253Sgblack@eecs.umich.edu disassemble(Addr pc, const SymbolTable *symtab) const; 646253Sgblack@eecs.umich.edu}; 656253Sgblack@eecs.umich.edu 666253Sgblack@eecs.umich.edu/** 676253Sgblack@eecs.umich.edu * Base class for branches (PC-relative control transfers), 686253Sgblack@eecs.umich.edu * conditional or unconditional. 696253Sgblack@eecs.umich.edu */ 706253Sgblack@eecs.umich.educlass Branch : public PCDependentDisassembly 716253Sgblack@eecs.umich.edu{ 726253Sgblack@eecs.umich.edu protected: 736253Sgblack@eecs.umich.edu /// target address (signed) Displacement . 746253Sgblack@eecs.umich.edu int32_t disp; 756253Sgblack@eecs.umich.edu 766253Sgblack@eecs.umich.edu /// Constructor. 777099Sgblack@eecs.umich.edu Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 786253Sgblack@eecs.umich.edu : PCDependentDisassembly(mnem, _machInst, __opClass), 796253Sgblack@eecs.umich.edu disp(machInst.offset << 2) 806253Sgblack@eecs.umich.edu { 816253Sgblack@eecs.umich.edu //If Bit 26 is 1 then Sign Extend 826253Sgblack@eecs.umich.edu if ( (disp & 0x02000000) > 0 ) { 836253Sgblack@eecs.umich.edu disp |= 0xFC000000; 846253Sgblack@eecs.umich.edu } 856253Sgblack@eecs.umich.edu } 866253Sgblack@eecs.umich.edu 876253Sgblack@eecs.umich.edu Addr branchTarget(Addr branchPC) const; 886253Sgblack@eecs.umich.edu 896253Sgblack@eecs.umich.edu std::string 906253Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 916253Sgblack@eecs.umich.edu}; 926253Sgblack@eecs.umich.edu 936253Sgblack@eecs.umich.edu/** 946253Sgblack@eecs.umich.edu * Base class for branch and exchange instructions on the ARM 956253Sgblack@eecs.umich.edu */ 966253Sgblack@eecs.umich.educlass BranchExchange : public PredOp 976253Sgblack@eecs.umich.edu{ 986253Sgblack@eecs.umich.edu protected: 996253Sgblack@eecs.umich.edu /// Constructor 1007099Sgblack@eecs.umich.edu BranchExchange(const char *mnem, ExtMachInst _machInst, 1016253Sgblack@eecs.umich.edu OpClass __opClass) 1026253Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass) 1036253Sgblack@eecs.umich.edu { 1046253Sgblack@eecs.umich.edu } 1056253Sgblack@eecs.umich.edu 1066253Sgblack@eecs.umich.edu std::string 1076253Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1086253Sgblack@eecs.umich.edu}; 1096253Sgblack@eecs.umich.edu 1106253Sgblack@eecs.umich.edu 1116253Sgblack@eecs.umich.edu/** 1126253Sgblack@eecs.umich.edu * Base class for jumps (register-indirect control transfers). In 1136253Sgblack@eecs.umich.edu * the Arm ISA, these are always unconditional. 1146253Sgblack@eecs.umich.edu */ 1156253Sgblack@eecs.umich.educlass Jump : public PCDependentDisassembly 1166253Sgblack@eecs.umich.edu{ 1176253Sgblack@eecs.umich.edu protected: 1186253Sgblack@eecs.umich.edu 1196253Sgblack@eecs.umich.edu /// Displacement to target address (signed). 1206253Sgblack@eecs.umich.edu int32_t disp; 1216253Sgblack@eecs.umich.edu 1226253Sgblack@eecs.umich.edu uint32_t target; 1236253Sgblack@eecs.umich.edu 1246253Sgblack@eecs.umich.edu public: 1256253Sgblack@eecs.umich.edu /// Constructor 1267099Sgblack@eecs.umich.edu Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 1276253Sgblack@eecs.umich.edu : PCDependentDisassembly(mnem, _machInst, __opClass), 1286253Sgblack@eecs.umich.edu disp(machInst.offset << 2) 1296253Sgblack@eecs.umich.edu { 1306253Sgblack@eecs.umich.edu } 1316253Sgblack@eecs.umich.edu 1326253Sgblack@eecs.umich.edu Addr branchTarget(ThreadContext *tc) const; 1336253Sgblack@eecs.umich.edu 1346253Sgblack@eecs.umich.edu std::string 1356253Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1366253Sgblack@eecs.umich.edu}; 1376253Sgblack@eecs.umich.edu} 1386253Sgblack@eecs.umich.edu 1396253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_BRANCH_HH__ 140