branch.cc revision 7144:097e00bcf084 
1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29
30#include "arch/arm/insts/branch.hh"
31#include "base/loader/symtab.hh"
32
33namespace ArmISA
34{
35Addr
36Branch::branchTarget(Addr branchPC) const
37{
38    return branchPC + 8 + disp;
39}
40
41const std::string &
42PCDependentDisassembly::disassemble(Addr pc,
43                                    const SymbolTable *symtab) const
44{
45    if (!cachedDisassembly ||
46        pc != cachedPC || symtab != cachedSymtab)
47    {
48        if (cachedDisassembly)
49            delete cachedDisassembly;
50
51        cachedDisassembly =
52            new std::string(generateDisassembly(pc, symtab));
53        cachedPC = pc;
54        cachedSymtab = symtab;
55    }
56
57    return *cachedDisassembly;
58}
59
60std::string
61Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
62{
63    std::stringstream ss;
64
65    printMnemonic(ss);
66    ss << "\t";
67
68    Addr target = pc + 8 + disp;
69    ccprintf(ss, "%#x", target);
70    printMemSymbol(ss, symtab, " <", target, ">");
71
72    return ss.str();
73}
74
75std::string
76BranchExchange::generateDisassembly(Addr pc, const SymbolTable *symtab) const
77{
78    std::stringstream ss;
79    printMnemonic(ss);
80    if (_numSrcRegs > 0) {
81        printReg(ss, _srcRegIdx[0]);
82    }
83    return ss.str();
84}
85}
86