faults.hh revision 8545:a3992291e230
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2010 ARM Limited 37100Sgblack@eecs.umich.edu * All rights reserved 47100Sgblack@eecs.umich.edu * 57100Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67100Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77100Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87100Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97100Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107100Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117100Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127100Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137100Sgblack@eecs.umich.edu * 147100Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Ali Saidi 426757SAli.Saidi@ARM.com * Gabe Black 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 466019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edu#include "arch/arm/miscregs.hh" 496019Shines@cs.fsu.edu#include "arch/arm/types.hh" 509022Sgblack@eecs.umich.edu#include "base/misc.hh" 516019Shines@cs.fsu.edu#include "config/full_system.hh" 527170Sgblack@eecs.umich.edu#include "sim/faults.hh" 536253Sgblack@eecs.umich.edu 547202Sgblack@eecs.umich.edu// The design of the "name" and "vect" functions is in sim/faults.hh 556253Sgblack@eecs.umich.edu 566253Sgblack@eecs.umich.edunamespace ArmISA 577396Sgblack@eecs.umich.edu{ 588745Sgblack@eecs.umich.edutypedef const Addr FaultOffset; 597405SAli.Saidi@ARM.com 608782Sgblack@eecs.umich.educlass ArmFault : public FaultBase 618782Sgblack@eecs.umich.edu{ 628782Sgblack@eecs.umich.edu protected: 637259Sgblack@eecs.umich.edu Addr getVector(ThreadContext *tc); 648757Sgblack@eecs.umich.edu 657423Sgblack@eecs.umich.edu public: 668782Sgblack@eecs.umich.edu enum StatusEncoding 678757Sgblack@eecs.umich.edu { 688777Sgblack@eecs.umich.edu // Fault Status register encodings 698782Sgblack@eecs.umich.edu // ARM ARM B3.9.4 708756Sgblack@eecs.umich.edu AlignmentFault = 0x1, 716019Shines@cs.fsu.edu DebugEvent = 0x2, 726757SAli.Saidi@ARM.com AccessFlag0 = 0x3, 738757Sgblack@eecs.umich.edu InstructionCacheMaintenance = 0x4, 746019Shines@cs.fsu.edu Translation0 = 0x5, 758745Sgblack@eecs.umich.edu AccessFlag1 = 0x6, 766397Sgblack@eecs.umich.edu Translation1 = 0x7, 778782Sgblack@eecs.umich.edu SynchronousExternalAbort0 = 0x8, 786019Shines@cs.fsu.edu Domain0 = 0x9, 796397Sgblack@eecs.umich.edu SynchronousExternalAbort1 = 0x8, 808335Snate@binkert.org Domain1 = 0xb, 818335Snate@binkert.org TranslationTableWalkExtAbt0 = 0xc, 828335Snate@binkert.org Permission0 = 0xd, 838335Snate@binkert.org TranslationTableWalkExtAbt1 = 0xe, 846019Shines@cs.fsu.edu Permission1 = 0xf, 856019Shines@cs.fsu.edu AsynchronousExternalAbort = 0x16, 866019Shines@cs.fsu.edu MemoryAccessAsynchronousParityError = 0x18, 876019Shines@cs.fsu.edu MemoryAccessSynchronousParityError = 0x19, 886019Shines@cs.fsu.edu TranslationTableWalkPrtyErr0 = 0x1c, 896019Shines@cs.fsu.edu TranslationTableWalkPrtyErr1 = 0x1e, 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.edu // not a real fault. This is a status code 92 // to allow the translation function to inform 93 // the memory access function not to proceed 94 // for a Prefetch that misses in the TLB. 95 PrefetchTLBMiss = 0x1f, 96 PrefetchUncacheable = 0x20 97 }; 98 99 struct FaultVals 100 { 101 const FaultName name; 102 const FaultOffset offset; 103 const OperatingMode nextMode; 104 const uint8_t armPcOffset; 105 const uint8_t thumbPcOffset; 106 const bool abortDisable; 107 const bool fiqDisable; 108 FaultStat count; 109 }; 110 111#if FULL_SYSTEM 112 void invoke(ThreadContext *tc, 113 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 114#endif 115 virtual FaultStat& countStat() = 0; 116 virtual FaultOffset offset() = 0; 117 virtual OperatingMode nextMode() = 0; 118 virtual uint8_t armPcOffset() = 0; 119 virtual uint8_t thumbPcOffset() = 0; 120 virtual bool abortDisable() = 0; 121 virtual bool fiqDisable() = 0; 122}; 123 124template<typename T> 125class ArmFaultVals : public ArmFault 126{ 127 protected: 128 static FaultVals vals; 129 130 public: 131 FaultName name() const { return vals.name; } 132 FaultStat & countStat() {return vals.count;} 133 FaultOffset offset() { return vals.offset; } 134 OperatingMode nextMode() { return vals.nextMode; } 135 uint8_t armPcOffset() { return vals.armPcOffset; } 136 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 137 bool abortDisable() { return vals.abortDisable; } 138 bool fiqDisable() { return vals.fiqDisable; } 139}; 140 141class Reset : public ArmFaultVals<Reset> 142#if FULL_SYSTEM 143{ 144 public: 145 void invoke(ThreadContext *tc, 146 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 147}; 148#else 149{}; 150#endif //FULL_SYSTEM 151 152class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 153{ 154#if !FULL_SYSTEM 155 protected: 156 ExtMachInst machInst; 157 bool unknown; 158 const char *mnemonic; 159 bool disabled; 160 161 public: 162 UndefinedInstruction(ExtMachInst _machInst, 163 bool _unknown, 164 const char *_mnemonic = NULL, 165 bool _disabled = false) : 166 machInst(_machInst), unknown(_unknown), 167 mnemonic(_mnemonic), disabled(_disabled) 168 { 169 } 170 171 void invoke(ThreadContext *tc, 172 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 173#endif 174}; 175 176class SupervisorCall : public ArmFaultVals<SupervisorCall> 177{ 178#if !FULL_SYSTEM 179 protected: 180 ExtMachInst machInst; 181 182 public: 183 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 184 {} 185 186 void invoke(ThreadContext *tc, 187 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 188#endif 189}; 190 191template <class T> 192class AbortFault : public ArmFaultVals<T> 193{ 194 protected: 195 Addr faultAddr; 196 bool write; 197 uint8_t domain; 198 uint8_t status; 199 200 public: 201 AbortFault(Addr _faultAddr, bool _write, 202 uint8_t _domain, uint8_t _status) : 203 faultAddr(_faultAddr), write(_write), 204 domain(_domain), status(_status) 205 {} 206 207 void invoke(ThreadContext *tc, 208 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 209}; 210 211class PrefetchAbort : public AbortFault<PrefetchAbort> 212{ 213 public: 214 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 215 static const MiscRegIndex FarIndex = MISCREG_IFAR; 216 217 PrefetchAbort(Addr _addr, uint8_t _status) : 218 AbortFault<PrefetchAbort>(_addr, false, 0, _status) 219 {} 220}; 221 222class DataAbort : public AbortFault<DataAbort> 223{ 224 public: 225 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 226 static const MiscRegIndex FarIndex = MISCREG_DFAR; 227 228 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 229 AbortFault<DataAbort>(_addr, _write, _domain, _status) 230 {} 231}; 232 233class Interrupt : public ArmFaultVals<Interrupt> {}; 234class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 235 236// A fault that flushes the pipe, excluding the faulting instructions 237class FlushPipe : public ArmFaultVals<FlushPipe> 238{ 239 public: 240 FlushPipe() {} 241 void invoke(ThreadContext *tc, 242 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 243}; 244 245static inline Fault genMachineCheckFault() 246{ 247 return new Reset(); 248} 249 250// A fault that flushes the pipe, excluding the faulting instructions 251class ArmSev : public ArmFaultVals<ArmSev> 252{ 253 public: 254 ArmSev () {} 255 void invoke(ThreadContext *tc, 256 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 257}; 258 259} // namespace ArmISA 260 261#endif // __ARM_FAULTS_HH__ 262