faults.hh revision 7611:c119da5a80c8 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#ifndef __ARM_FAULTS_HH__
46#define __ARM_FAULTS_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "config/full_system.hh"
51#include "sim/faults.hh"
52#include "base/misc.hh"
53
54// The design of the "name" and "vect" functions is in sim/faults.hh
55
56namespace ArmISA
57{
58typedef const Addr FaultOffset;
59
60class ArmFault : public FaultBase
61{
62  protected:
63    Addr getVector(ThreadContext *tc);
64
65  public:
66    enum StatusEncoding
67    {
68        // Fault Status register encodings
69        // ARM ARM B3.9.4
70        AlignmentFault = 0x1,
71        DebugEvent = 0x2,
72        AccessFlag0 = 0x3,
73        InstructionCacheMaintenance = 0x4,
74        Translation0 = 0x5,
75        AccessFlag1 = 0x6,
76        Translation1 = 0x7,
77        SynchronousExternalAbort0 = 0x8,
78        Domain0 = 0x9,
79        SynchronousExternalAbort1 = 0x8,
80        Domain1 = 0xb,
81        TranslationTableWalkExtAbt0 = 0xc,
82        Permission0 = 0xd,
83        TranslationTableWalkExtAbt1 = 0xe,
84        Permission1 = 0xf,
85        AsynchronousExternalAbort = 0x16,
86        MemoryAccessAsynchronousParityError = 0x18,
87        MemoryAccessSynchronousParityError = 0x19,
88        TranslationTableWalkPrtyErr0 = 0x1c,
89        TranslationTableWalkPrtyErr1 = 0x1e,
90
91        // not a real fault. This is a status code
92        // to allow the translation function to inform
93        // the memory access function not to proceed
94        // for a Prefetch that misses in the TLB.
95        PrefetchTLBMiss
96    };
97
98    struct FaultVals
99    {
100        const FaultName name;
101        const FaultOffset offset;
102        const OperatingMode nextMode;
103        const uint8_t armPcOffset;
104        const uint8_t thumbPcOffset;
105        const bool abortDisable;
106        const bool fiqDisable;
107        FaultStat count;
108    };
109
110#if FULL_SYSTEM
111    void invoke(ThreadContext *tc);
112#endif
113    virtual FaultStat& countStat() = 0;
114    virtual FaultOffset offset() = 0;
115    virtual OperatingMode nextMode() = 0;
116    virtual uint8_t armPcOffset() = 0;
117    virtual uint8_t thumbPcOffset() = 0;
118    virtual bool abortDisable() = 0;
119    virtual bool fiqDisable() = 0;
120};
121
122template<typename T>
123class ArmFaultVals : public ArmFault
124{
125  protected:
126    static FaultVals vals;
127
128  public:
129    FaultName name() const { return vals.name; }
130    FaultStat & countStat() {return vals.count;}
131    FaultOffset offset() { return vals.offset; }
132    OperatingMode nextMode() { return vals.nextMode; }
133    uint8_t armPcOffset() { return vals.armPcOffset; }
134    uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
135    bool abortDisable() { return vals.abortDisable; }
136    bool fiqDisable() { return vals.fiqDisable; }
137};
138
139class Reset : public ArmFaultVals<Reset>
140#if FULL_SYSTEM
141{
142  public:
143    void invoke(ThreadContext *tc);
144};
145#else
146{};
147#endif //FULL_SYSTEM
148
149class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
150{
151#if !FULL_SYSTEM
152  protected:
153    ExtMachInst machInst;
154    bool unknown;
155    const char *mnemonic;
156
157  public:
158    UndefinedInstruction(ExtMachInst _machInst,
159                         bool _unknown,
160                         const char *_mnemonic = NULL) :
161        machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic)
162    {
163    }
164
165    void invoke(ThreadContext *tc);
166#endif
167};
168
169class SupervisorCall : public ArmFaultVals<SupervisorCall>
170{
171#if !FULL_SYSTEM
172  protected:
173    ExtMachInst machInst;
174
175  public:
176    SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
177    {}
178
179    void invoke(ThreadContext *tc);
180#endif
181};
182
183template <class T>
184class AbortFault : public ArmFaultVals<T>
185{
186  protected:
187    Addr faultAddr;
188    bool write;
189    uint8_t domain;
190    uint8_t status;
191
192  public:
193    AbortFault(Addr _faultAddr, bool _write,
194            uint8_t _domain, uint8_t _status) :
195        faultAddr(_faultAddr), write(_write),
196        domain(_domain), status(_status)
197    {}
198
199    void invoke(ThreadContext *tc);
200};
201
202class PrefetchAbort : public AbortFault<PrefetchAbort>
203{
204  public:
205    static const MiscRegIndex FsrIndex = MISCREG_IFSR;
206    static const MiscRegIndex FarIndex = MISCREG_IFAR;
207
208    PrefetchAbort(Addr _addr, uint8_t _status) :
209        AbortFault<PrefetchAbort>(_addr, false, 0, _status)
210    {}
211};
212
213class DataAbort : public AbortFault<DataAbort>
214{
215  public:
216    static const MiscRegIndex FsrIndex = MISCREG_DFSR;
217    static const MiscRegIndex FarIndex = MISCREG_DFAR;
218
219    DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) :
220        AbortFault<DataAbort>(_addr, _write, _domain, _status)
221    {}
222};
223
224class Interrupt : public ArmFaultVals<Interrupt> {};
225class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
226
227static inline Fault genMachineCheckFault()
228{
229    return new Reset();
230}
231
232} // ArmISA namespace
233
234#endif // __ARM_FAULTS_HH__
235