faults.hh revision 7595:65d88997f738 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#ifndef __ARM_FAULTS_HH__
46#define __ARM_FAULTS_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "config/full_system.hh"
51#include "sim/faults.hh"
52
53// The design of the "name" and "vect" functions is in sim/faults.hh
54
55namespace ArmISA
56{
57typedef const Addr FaultOffset;
58
59class ArmFault : public FaultBase
60{
61  protected:
62    Addr getVector(ThreadContext *tc);
63
64  public:
65    enum StatusEncoding
66    {
67        // Fault Status register encodings
68        // ARM ARM B3.9.4
69        AlignmentFault = 0x1,
70        DebugEvent = 0x2,
71        AccessFlag0 = 0x3,
72        InstructionCacheMaintenance = 0x4,
73        Translation0 = 0x5,
74        AccessFlag1 = 0x6,
75        Translation1 = 0x7,
76        SynchronousExternalAbort0 = 0x8,
77        Domain0 = 0x9,
78        SynchronousExternalAbort1 = 0x8,
79        Domain1 = 0xb,
80        TranslationTableWalkExtAbt0 = 0xc,
81        Permission0 = 0xd,
82        TranslationTableWalkExtAbt1 = 0xe,
83        Permission1 = 0xf,
84        AsynchronousExternalAbort = 0x16,
85        MemoryAccessAsynchronousParityError = 0x18,
86        MemoryAccessSynchronousParityError = 0x19,
87        TranslationTableWalkPrtyErr0 = 0x1c,
88        TranslationTableWalkPrtyErr1 = 0x1e,
89    };
90
91    struct FaultVals
92    {
93        const FaultName name;
94        const FaultOffset offset;
95        const OperatingMode nextMode;
96        const uint8_t armPcOffset;
97        const uint8_t thumbPcOffset;
98        const bool abortDisable;
99        const bool fiqDisable;
100        FaultStat count;
101    };
102
103#if FULL_SYSTEM
104    void invoke(ThreadContext *tc);
105#endif
106    virtual FaultStat& countStat() = 0;
107    virtual FaultOffset offset() = 0;
108    virtual OperatingMode nextMode() = 0;
109    virtual uint8_t armPcOffset() = 0;
110    virtual uint8_t thumbPcOffset() = 0;
111    virtual bool abortDisable() = 0;
112    virtual bool fiqDisable() = 0;
113};
114
115template<typename T>
116class ArmFaultVals : public ArmFault
117{
118  protected:
119    static FaultVals vals;
120
121  public:
122    FaultName name() const { return vals.name; }
123    FaultStat & countStat() {return vals.count;}
124    FaultOffset offset() { return vals.offset; }
125    OperatingMode nextMode() { return vals.nextMode; }
126    uint8_t armPcOffset() { return vals.armPcOffset; }
127    uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
128    bool abortDisable() { return vals.abortDisable; }
129    bool fiqDisable() { return vals.fiqDisable; }
130};
131
132class Reset : public ArmFaultVals<Reset>
133#if FULL_SYSTEM
134{
135  public:
136    void invoke(ThreadContext *tc);
137};
138#else
139{};
140#endif //FULL_SYSTEM
141
142class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
143{
144#if !FULL_SYSTEM
145  protected:
146    ExtMachInst machInst;
147    bool unknown;
148    const char *mnemonic;
149
150  public:
151    UndefinedInstruction(ExtMachInst _machInst,
152                         bool _unknown,
153                         const char *_mnemonic = NULL) :
154        machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic)
155    {
156    }
157
158    void invoke(ThreadContext *tc);
159#endif
160};
161
162class SupervisorCall : public ArmFaultVals<SupervisorCall>
163{
164#if !FULL_SYSTEM
165  protected:
166    ExtMachInst machInst;
167
168  public:
169    SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
170    {}
171
172    void invoke(ThreadContext *tc);
173#endif
174};
175
176template <class T>
177class AbortFault : public ArmFaultVals<T>
178{
179  protected:
180    Addr faultAddr;
181    bool write;
182    uint8_t domain;
183    uint8_t status;
184
185  public:
186    AbortFault(Addr _faultAddr, bool _write,
187            uint8_t _domain, uint8_t _status) :
188        faultAddr(_faultAddr), write(_write),
189        domain(_domain), status(_status)
190    {}
191
192    void invoke(ThreadContext *tc);
193};
194
195class PrefetchAbort : public AbortFault<PrefetchAbort>
196{
197  public:
198    static const MiscRegIndex FsrIndex = MISCREG_IFSR;
199    static const MiscRegIndex FarIndex = MISCREG_IFAR;
200
201    PrefetchAbort(Addr _addr, uint8_t _status) :
202        AbortFault<PrefetchAbort>(_addr, false, 0, _status)
203    {}
204};
205
206class DataAbort : public AbortFault<DataAbort>
207{
208  public:
209    static const MiscRegIndex FsrIndex = MISCREG_DFSR;
210    static const MiscRegIndex FarIndex = MISCREG_DFAR;
211
212    DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) :
213        AbortFault<DataAbort>(_addr, _write, _domain, _status)
214    {}
215};
216
217class Interrupt : public ArmFaultVals<Interrupt> {};
218class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
219
220
221} // ArmISA namespace
222
223#endif // __ARM_FAULTS_HH__
224