faults.hh revision 7400:f6c9b27c4dbe 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#ifndef __ARM_FAULTS_HH__
46#define __ARM_FAULTS_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "config/full_system.hh"
51#include "sim/faults.hh"
52
53// The design of the "name" and "vect" functions is in sim/faults.hh
54
55namespace ArmISA
56{
57typedef const Addr FaultOffset;
58
59class ArmFault : public FaultBase
60{
61  protected:
62    Addr getVector(ThreadContext *tc);
63
64  public:
65    enum StatusEncoding
66    {
67        // Fault Status register encodings
68        // ARM ARM B3.9.4
69        AlignmentFault = 0x1,
70        DebugEvent = 0x2,
71        AccessFlag0 = 0x3,
72        InstructionCacheMaintenance = 0x4,
73        Translation0 = 0x5,
74        AccessFlag1 = 0x6,
75        Translation1 = 0x7,
76        SynchronousExternalAbort0 = 0x8,
77        Domain0 = 0x9,
78        Domain1 = 0xb,
79        TranslationTableWalk0 = 0xc,
80        Permission0 = 0xd,
81        SynchronousExternalAbort1 = 0xe,
82        Permission1 = 0xf,
83        AsynchronousExternalAbort = 0x16,
84        MemoryAccessAsynchronousParityError = 0x18,
85        MemoryAccessSynchronousParityError = 0x19,
86        TranslationTableWalk1 = 0x1c,
87        SynchronousParityError = 0x1e
88    };
89
90    struct FaultVals
91    {
92        const FaultName name;
93        const FaultOffset offset;
94        const OperatingMode nextMode;
95        const uint8_t armPcOffset;
96        const uint8_t thumbPcOffset;
97        const bool abortDisable;
98        const bool fiqDisable;
99        FaultStat count;
100    };
101
102#if FULL_SYSTEM
103    void invoke(ThreadContext *tc);
104#endif
105    virtual FaultStat& countStat() = 0;
106    virtual FaultOffset offset() = 0;
107    virtual OperatingMode nextMode() = 0;
108    virtual uint8_t armPcOffset() = 0;
109    virtual uint8_t thumbPcOffset() = 0;
110    virtual bool abortDisable() = 0;
111    virtual bool fiqDisable() = 0;
112};
113
114template<typename T>
115class ArmFaultVals : public ArmFault
116{
117  protected:
118    static FaultVals vals;
119
120  public:
121    FaultName name() const { return vals.name; }
122    FaultStat & countStat() {return vals.count;}
123    FaultOffset offset() { return vals.offset; }
124    OperatingMode nextMode() { return vals.nextMode; }
125    uint8_t armPcOffset() { return vals.armPcOffset; }
126    uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
127    bool abortDisable() { return vals.abortDisable; }
128    bool fiqDisable() { return vals.fiqDisable; }
129};
130
131class Reset : public ArmFaultVals<Reset>
132#if FULL_SYSTEM
133{
134  public:
135    void invoke(ThreadContext *tc);
136};
137#else
138{};
139#endif //FULL_SYSTEM
140
141class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
142{
143#if !FULL_SYSTEM
144  protected:
145    ExtMachInst machInst;
146    bool unknown;
147    const char *mnemonic;
148
149  public:
150    UndefinedInstruction(ExtMachInst _machInst,
151                         bool _unknown,
152                         const char *_mnemonic = NULL) :
153        machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic)
154    {
155    }
156
157    void invoke(ThreadContext *tc);
158#endif
159};
160
161class SupervisorCall : public ArmFaultVals<SupervisorCall>
162{
163#if !FULL_SYSTEM
164  protected:
165    ExtMachInst machInst;
166
167  public:
168    SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
169    {}
170
171    void invoke(ThreadContext *tc);
172#endif
173};
174
175template <class T>
176class AbortFault : public ArmFaultVals<T>
177{
178  protected:
179    Addr faultAddr;
180    bool write;
181    uint8_t domain;
182    uint8_t status;
183
184  public:
185    AbortFault(Addr _faultAddr, bool _write,
186            uint8_t _domain, uint8_t _status) :
187        faultAddr(_faultAddr), write(_write),
188        domain(_domain), status(_status)
189    {}
190
191    void invoke(ThreadContext *tc);
192};
193
194class PrefetchAbort : public AbortFault<PrefetchAbort>
195{
196  public:
197    static const MiscRegIndex FsrIndex = MISCREG_IFSR;
198    static const MiscRegIndex FarIndex = MISCREG_IFAR;
199
200    PrefetchAbort(Addr _addr, uint8_t _status) :
201        AbortFault<PrefetchAbort>(_addr, false, 0, _status)
202    {}
203};
204
205class DataAbort : public AbortFault<DataAbort>
206{
207  public:
208    static const MiscRegIndex FsrIndex = MISCREG_DFSR;
209    static const MiscRegIndex FarIndex = MISCREG_DFAR;
210
211    DataAbort(Addr _addr, bool _write, uint8_t _domain, uint8_t _status) :
212        AbortFault<DataAbort>(_addr, _write, _domain, _status)
213    {}
214};
215
216class Interrupt : public ArmFaultVals<Interrupt> {};
217class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
218
219
220} // ArmISA namespace
221
222#endif // __ARM_FAULTS_HH__
223