faults.hh revision 7189:28998288c48b
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 48#include "arch/arm/types.hh" 49#include "config/full_system.hh" 50#include "sim/faults.hh" 51 52// The design of the "name" and "vect" functions is in sim/faults.hh 53 54namespace ArmISA 55{ 56typedef const Addr FaultOffset; 57 58class ArmFaultBase : public FaultBase 59{ 60 protected: 61 Addr getVector(ThreadContext *tc); 62 63 public: 64 struct FaultVals 65 { 66 const FaultName name; 67 const FaultOffset offset; 68 const OperatingMode nextMode; 69 const uint8_t armPcOffset; 70 const uint8_t thumbPcOffset; 71 const bool abortDisable; 72 const bool fiqDisable; 73 FaultStat count; 74 }; 75 76#if FULL_SYSTEM 77 void invoke(ThreadContext *tc); 78#endif 79 virtual FaultStat& countStat() = 0; 80 virtual FaultOffset offset() = 0; 81 virtual OperatingMode nextMode() = 0; 82 virtual uint8_t armPcOffset() = 0; 83 virtual uint8_t thumbPcOffset() = 0; 84 virtual bool abortDisable() = 0; 85 virtual bool fiqDisable() = 0; 86}; 87 88template<typename T> 89class ArmFault : public ArmFaultBase 90{ 91 protected: 92 static FaultVals vals; 93 94 public: 95 FaultName name() const { return vals.name; } 96 FaultStat & countStat() {return vals.count;} 97 FaultOffset offset() { return vals.offset; } 98 OperatingMode nextMode() { return vals.nextMode; } 99 uint8_t armPcOffset() { return vals.armPcOffset; } 100 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 101 bool abortDisable() { return vals.abortDisable; } 102 bool fiqDisable() { return vals.fiqDisable; } 103}; 104 105 106class Reset : public ArmFault<Reset> {}; 107 108class UndefinedInstruction : public ArmFault<UndefinedInstruction> 109{ 110#if !FULL_SYSTEM 111 protected: 112 ExtMachInst machInst; 113 bool unknown; 114 const char *mnemonic; 115 116 public: 117 UndefinedInstruction(ExtMachInst _machInst, 118 bool _unknown, 119 const char *_mnemonic = NULL) : 120 machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic) 121 { 122 } 123 124 void invoke(ThreadContext *tc); 125#endif 126}; 127 128class SupervisorCall : public ArmFault<SupervisorCall> {}; 129class PrefetchAbort : public ArmFault<PrefetchAbort> {}; 130class DataAbort : public ArmFault<DataAbort> {}; 131class Interrupt : public ArmFault<Interrupt> {}; 132class FastInterrupt : public ArmFault<FastInterrupt> {}; 133 134 135} // ArmISA namespace 136 137#endif // __ARM_FAULTS_HH__ 138