faults.hh revision 6735:6437ad24a8a0 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 *          Gabe Black
31 */
32
33#ifndef __ARM_FAULTS_HH__
34#define __ARM_FAULTS_HH__
35
36#include "arch/arm/types.hh"
37#include "config/full_system.hh"
38#include "sim/faults.hh"
39
40// The design of the "name" and "vect" functions is in sim/faults.hh
41
42namespace ArmISA
43{
44typedef const Addr FaultOffset;
45
46class ArmFaultBase : public FaultBase
47{
48  protected:
49    Addr getVector(ThreadContext *tc);
50
51  public:
52    struct FaultVals
53    {
54        const FaultName name;
55        const FaultOffset offset;
56        const OperatingMode nextMode;
57        const uint8_t armPcOffset;
58        const uint8_t thumbPcOffset;
59        const bool abortDisable;
60        const bool fiqDisable;
61        FaultStat count;
62    };
63
64#if FULL_SYSTEM
65    void invoke(ThreadContext *tc);
66#endif
67    virtual FaultStat& countStat() = 0;
68    virtual FaultOffset offset() = 0;
69    virtual OperatingMode nextMode() = 0;
70    virtual uint8_t armPcOffset() = 0;
71    virtual uint8_t thumbPcOffset() = 0;
72    virtual bool abortDisable() = 0;
73    virtual bool fiqDisable() = 0;
74};
75
76template<typename T>
77class ArmFault : public ArmFaultBase
78{
79  protected:
80    static FaultVals vals;
81
82  public:
83    FaultName name() const { return vals.name; }
84    FaultStat & countStat() {return vals.count;}
85    FaultOffset offset() { return vals.offset; }
86    OperatingMode nextMode() { return vals.nextMode; }
87    uint8_t armPcOffset() { return vals.armPcOffset; }
88    uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
89    bool abortDisable() { return vals.abortDisable; }
90    bool fiqDisable() { return vals.fiqDisable; }
91};
92
93
94class Reset                : public ArmFault<Reset> {};
95class UndefinedInstruction : public ArmFault<UndefinedInstruction> {};
96class SupervisorCall       : public ArmFault<SupervisorCall> {};
97class PrefetchAbort        : public ArmFault<PrefetchAbort> {};
98class DataAbort            : public ArmFault<DataAbort> {};
99class Interrupt            : public ArmFault<Interrupt> {};
100class FastInterrupt        : public ArmFault<FastInterrupt> {};
101
102
103} // ArmISA namespace
104
105#endif // __ARM_FAULTS_HH__
106