faults.hh revision 13456:a0914e5cbc7a
1/* 2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 * Giacomo Gabrielli 44 * Thomas Grocutt 45 */ 46 47#ifndef __ARM_FAULTS_HH__ 48#define __ARM_FAULTS_HH__ 49 50#include "arch/arm/miscregs.hh" 51#include "arch/arm/pagetable.hh" 52#include "arch/arm/types.hh" 53#include "base/logging.hh" 54#include "sim/faults.hh" 55#include "sim/full_system.hh" 56 57// The design of the "name" and "vect" functions is in sim/faults.hh 58 59namespace ArmISA 60{ 61typedef Addr FaultOffset; 62 63class ArmFault : public FaultBase 64{ 65 protected: 66 ExtMachInst machInst; 67 uint32_t issRaw; 68 69 // Helper variables for ARMv8 exception handling 70 bool from64; // True if the exception is generated from the AArch64 state 71 bool to64; // True if the exception is taken in AArch64 state 72 ExceptionLevel fromEL; // Source exception level 73 ExceptionLevel toEL; // Target exception level 74 OperatingMode fromMode; // Source operating mode (aarch32) 75 OperatingMode toMode; // Next operating mode (aarch32) 76 77 // This variable is true if the above fault specific informations 78 // have been updated. This is to prevent that a client is using their 79 // un-updated default constructed value. 80 bool faultUpdated; 81 82 bool hypRouted; // True if the fault has been routed to Hypervisor 83 84 virtual Addr getVector(ThreadContext *tc); 85 Addr getVector64(ThreadContext *tc); 86 87 public: 88 /// Generic fault source enums used to index into 89 /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 90 /// on the current register width state and the translation table format in 91 /// use 92 enum FaultSource 93 { 94 AlignmentFault = 0, 95 InstructionCacheMaintenance, // Short-desc. format only 96 SynchExtAbtOnTranslTableWalkLL, 97 SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 98 TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 99 AccessFlagLL = TranslationLL + 4, 100 DomainLL = AccessFlagLL + 4, 101 PermissionLL = DomainLL + 4, 102 DebugEvent = PermissionLL + 4, 103 SynchronousExternalAbort, 104 TLBConflictAbort, // Requires LPAE 105 SynchPtyErrOnMemoryAccess, 106 AsynchronousExternalAbort, 107 AsynchPtyErrOnMemoryAccess, 108 AddressSizeLL, // AArch64 only 109 110 // Not real faults. These are faults to allow the translation function 111 // to inform the memory access function not to proceed for a prefetch 112 // that misses in the TLB or that targets an uncacheable address 113 PrefetchTLBMiss = AddressSizeLL + 4, 114 PrefetchUncacheable, 115 116 NumFaultSources, 117 FaultSourceInvalid = 0xff 118 }; 119 120 /// Encodings of the fault sources when the short-desc. translation table 121 /// format is in use (ARM ARM Issue C B3.13.3) 122 static uint8_t shortDescFaultSources[NumFaultSources]; 123 /// Encodings of the fault sources when the long-desc. translation table 124 /// format is in use (ARM ARM Issue C B3.13.3) 125 static uint8_t longDescFaultSources[NumFaultSources]; 126 /// Encodings of the fault sources in AArch64 state 127 static uint8_t aarch64FaultSources[NumFaultSources]; 128 129 enum AnnotationIDs 130 { 131 S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 132 OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 133 SAS, // DataAbort: Syndrome Access Size 134 SSE, // DataAbort: Syndrome Sign Extend 135 SRT, // DataAbort: Syndrome Register Transfer 136 137 // AArch64 only 138 SF, // DataAbort: width of the accessed register is SixtyFour 139 AR // DataAbort: Acquire/Release semantics 140 }; 141 142 enum TranMethod 143 { 144 LpaeTran, 145 VmsaTran, 146 UnknownTran 147 }; 148 149 struct FaultVals 150 { 151 const FaultName name; 152 153 const FaultOffset offset; 154 155 // Offsets used for exceptions taken in AArch64 state 156 const uint16_t currELTOffset; 157 const uint16_t currELHOffset; 158 const uint16_t lowerEL64Offset; 159 const uint16_t lowerEL32Offset; 160 161 const OperatingMode nextMode; 162 163 const uint8_t armPcOffset; 164 const uint8_t thumbPcOffset; 165 // The following two values are used in place of armPcOffset and 166 // thumbPcOffset when the exception return address is saved into ELR 167 // registers (exceptions taken in HYP mode or in AArch64 state) 168 const uint8_t armPcElrOffset; 169 const uint8_t thumbPcElrOffset; 170 171 const bool hypTrappable; 172 const bool abortDisable; 173 const bool fiqDisable; 174 175 // Exception class used to appropriately set the syndrome register 176 // (exceptions taken in HYP mode or in AArch64 state) 177 const ExceptionClass ec; 178 179 FaultStat count; 180 FaultVals(const FaultName& name_, const FaultOffset& offset_, 181 const uint16_t& currELTOffset_, const uint16_t& currELHOffset_, 182 const uint16_t& lowerEL64Offset_, 183 const uint16_t& lowerEL32Offset_, 184 const OperatingMode& nextMode_, const uint8_t& armPcOffset_, 185 const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_, 186 const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_, 187 const bool& abortDisable_, const bool& fiqDisable_, 188 const ExceptionClass& ec_) 189 : name(name_), offset(offset_), currELTOffset(currELTOffset_), 190 currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_), 191 lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_), 192 armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_), 193 armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_), 194 hypTrappable(hypTrappable_), abortDisable(abortDisable_), 195 fiqDisable(fiqDisable_), ec(ec_) {} 196 }; 197 198 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 199 machInst(_machInst), issRaw(_iss), from64(false), to64(false), 200 fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), 201 faultUpdated(false), hypRouted(false) {} 202 203 // Returns the actual syndrome register to use based on the target 204 // exception level 205 MiscRegIndex getSyndromeReg64() const; 206 // Returns the actual fault address register to use based on the target 207 // exception level 208 MiscRegIndex getFaultAddrReg64() const; 209 210 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 211 StaticInst::nullStaticInstPtr) override; 212 void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 213 StaticInst::nullStaticInstPtr); 214 void update(ThreadContext *tc); 215 virtual void annotate(AnnotationIDs id, uint64_t val) {} 216 virtual FaultStat& countStat() = 0; 217 virtual FaultOffset offset(ThreadContext *tc) = 0; 218 virtual FaultOffset offset64(ThreadContext *tc) = 0; 219 virtual OperatingMode nextMode() = 0; 220 virtual bool routeToMonitor(ThreadContext *tc) const = 0; 221 virtual bool routeToHyp(ThreadContext *tc) const { return false; } 222 virtual uint8_t armPcOffset(bool isHyp) = 0; 223 virtual uint8_t thumbPcOffset(bool isHyp) = 0; 224 virtual uint8_t armPcElrOffset() = 0; 225 virtual uint8_t thumbPcElrOffset() = 0; 226 virtual bool abortDisable(ThreadContext *tc) = 0; 227 virtual bool fiqDisable(ThreadContext *tc) = 0; 228 virtual ExceptionClass ec(ThreadContext *tc) const = 0; 229 virtual uint32_t iss() const = 0; 230 virtual bool isStage2() const { return false; } 231 virtual FSR getFsr(ThreadContext *tc) const { return 0; } 232 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 233}; 234 235template<typename T> 236class ArmFaultVals : public ArmFault 237{ 238 protected: 239 static FaultVals vals; 240 241 public: 242 ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 243 ArmFault(_machInst, _iss) {} 244 FaultName name() const override { return vals.name; } 245 FaultStat & countStat() override { return vals.count; } 246 FaultOffset offset(ThreadContext *tc) override; 247 248 FaultOffset offset64(ThreadContext *tc) override; 249 250 OperatingMode nextMode() override { return vals.nextMode; } 251 virtual bool routeToMonitor(ThreadContext *tc) const override { 252 return false; 253 } 254 uint8_t armPcOffset(bool isHyp) override { 255 return isHyp ? vals.armPcElrOffset 256 : vals.armPcOffset; 257 } 258 uint8_t thumbPcOffset(bool isHyp) override { 259 return isHyp ? vals.thumbPcElrOffset 260 : vals.thumbPcOffset; 261 } 262 uint8_t armPcElrOffset() override { return vals.armPcElrOffset; } 263 uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; } 264 bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; } 265 bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; } 266 ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; } 267 uint32_t iss() const override { return issRaw; } 268}; 269 270class Reset : public ArmFaultVals<Reset> 271{ 272 protected: 273 Addr getVector(ThreadContext *tc) override; 274 275 public: 276 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 277 StaticInst::nullStaticInstPtr) override; 278}; 279 280class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 281{ 282 protected: 283 bool unknown; 284 bool disabled; 285 ExceptionClass overrideEc; 286 const char *mnemonic; 287 288 public: 289 UndefinedInstruction(ExtMachInst _machInst, 290 bool _unknown, 291 const char *_mnemonic = NULL, 292 bool _disabled = false) : 293 ArmFaultVals<UndefinedInstruction>(_machInst), 294 unknown(_unknown), disabled(_disabled), 295 overrideEc(EC_INVALID), mnemonic(_mnemonic) 296 {} 297 UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 298 ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 299 ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 300 unknown(false), disabled(true), overrideEc(_overrideEc), 301 mnemonic(_mnemonic) 302 {} 303 304 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 305 StaticInst::nullStaticInstPtr) override; 306 bool routeToHyp(ThreadContext *tc) const override; 307 ExceptionClass ec(ThreadContext *tc) const override; 308 uint32_t iss() const override; 309}; 310 311class SupervisorCall : public ArmFaultVals<SupervisorCall> 312{ 313 protected: 314 ExceptionClass overrideEc; 315 public: 316 SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 317 ExceptionClass _overrideEc = EC_INVALID) : 318 ArmFaultVals<SupervisorCall>(_machInst, _iss), 319 overrideEc(_overrideEc) 320 {} 321 322 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 323 StaticInst::nullStaticInstPtr) override; 324 bool routeToHyp(ThreadContext *tc) const override; 325 ExceptionClass ec(ThreadContext *tc) const override; 326 uint32_t iss() const override; 327}; 328 329class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 330{ 331 public: 332 SecureMonitorCall(ExtMachInst _machInst) : 333 ArmFaultVals<SecureMonitorCall>(_machInst) 334 {} 335 336 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 337 StaticInst::nullStaticInstPtr) override; 338 ExceptionClass ec(ThreadContext *tc) const override; 339 uint32_t iss() const override; 340}; 341 342class SupervisorTrap : public ArmFaultVals<SupervisorTrap> 343{ 344 protected: 345 ExtMachInst machInst; 346 ExceptionClass overrideEc; 347 348 public: 349 SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 350 ExceptionClass _overrideEc = EC_INVALID) : 351 ArmFaultVals<SupervisorTrap>(_machInst, _iss), 352 overrideEc(_overrideEc) 353 {} 354 355 bool routeToHyp(ThreadContext *tc) const override; 356 uint32_t iss() const override; 357 ExceptionClass ec(ThreadContext *tc) const override; 358}; 359 360class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 361{ 362 protected: 363 ExtMachInst machInst; 364 ExceptionClass overrideEc; 365 366 public: 367 SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 368 ExceptionClass _overrideEc = EC_INVALID) : 369 ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 370 overrideEc(_overrideEc) 371 {} 372 373 ExceptionClass ec(ThreadContext *tc) const override; 374}; 375 376class HypervisorCall : public ArmFaultVals<HypervisorCall> 377{ 378 public: 379 HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 380 381 ExceptionClass ec(ThreadContext *tc) const override; 382}; 383 384class HypervisorTrap : public ArmFaultVals<HypervisorTrap> 385{ 386 protected: 387 ExtMachInst machInst; 388 ExceptionClass overrideEc; 389 390 public: 391 HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 392 ExceptionClass _overrideEc = EC_INVALID) : 393 ArmFaultVals<HypervisorTrap>(_machInst, _iss), 394 overrideEc(_overrideEc) 395 {} 396 397 ExceptionClass ec(ThreadContext *tc) const override; 398}; 399 400template <class T> 401class AbortFault : public ArmFaultVals<T> 402{ 403 protected: 404 /** 405 * The virtual address the fault occured at. If 2 stages of 406 * translation are being used then this is the intermediate 407 * physical address that is the starting point for the second 408 * stage of translation. 409 */ 410 Addr faultAddr; 411 /** 412 * Original virtual address. If the fault was generated on the 413 * second stage of translation then this variable stores the 414 * virtual address used in the original stage 1 translation. 415 */ 416 Addr OVAddr; 417 bool write; 418 TlbEntry::DomainType domain; 419 uint8_t source; 420 uint8_t srcEncoded; 421 bool stage2; 422 bool s1ptw; 423 ArmFault::TranMethod tranMethod; 424 425 public: 426 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, 427 uint8_t _source, bool _stage2, 428 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 429 faultAddr(_faultAddr), OVAddr(0), write(_write), 430 domain(_domain), source(_source), srcEncoded(0), 431 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 432 {} 433 434 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 435 StaticInst::nullStaticInstPtr) override; 436 437 FSR getFsr(ThreadContext *tc) const override; 438 uint8_t getFaultStatusCode(ThreadContext *tc) const; 439 bool abortDisable(ThreadContext *tc) override; 440 uint32_t iss() const override; 441 bool isStage2() const override { return stage2; } 442 void annotate(ArmFault::AnnotationIDs id, uint64_t val) override; 443 void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override; 444 bool isMMUFault() const; 445}; 446 447class PrefetchAbort : public AbortFault<PrefetchAbort> 448{ 449 public: 450 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 451 static const MiscRegIndex FarIndex = MISCREG_IFAR; 452 static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 453 454 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 455 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 456 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 457 _source, _stage2, _tranMethod) 458 {} 459 460 ExceptionClass ec(ThreadContext *tc) const override; 461 // @todo: external aborts should be routed if SCR.EA == 1 462 bool routeToMonitor(ThreadContext *tc) const override; 463 bool routeToHyp(ThreadContext *tc) const override; 464}; 465 466class DataAbort : public AbortFault<DataAbort> 467{ 468 public: 469 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 470 static const MiscRegIndex FarIndex = MISCREG_DFAR; 471 static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 472 bool isv; 473 uint8_t sas; 474 uint8_t sse; 475 uint8_t srt; 476 477 // AArch64 only 478 bool sf; 479 bool ar; 480 481 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 482 bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 483 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 484 _tranMethod), 485 isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 486 {} 487 488 ExceptionClass ec(ThreadContext *tc) const override; 489 // @todo: external aborts should be routed if SCR.EA == 1 490 bool routeToMonitor(ThreadContext *tc) const override; 491 bool routeToHyp(ThreadContext *tc) const override; 492 uint32_t iss() const override; 493 void annotate(AnnotationIDs id, uint64_t val) override; 494}; 495 496class VirtualDataAbort : public AbortFault<VirtualDataAbort> 497{ 498 public: 499 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 500 static const MiscRegIndex FarIndex = MISCREG_DFAR; 501 static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 502 503 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 504 uint8_t _source) : 505 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 506 {} 507 508 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 509}; 510 511class Interrupt : public ArmFaultVals<Interrupt> 512{ 513 public: 514 bool routeToMonitor(ThreadContext *tc) const override; 515 bool routeToHyp(ThreadContext *tc) const override; 516 bool abortDisable(ThreadContext *tc) override; 517}; 518 519class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 520{ 521 public: 522 VirtualInterrupt(); 523}; 524 525class FastInterrupt : public ArmFaultVals<FastInterrupt> 526{ 527 public: 528 bool routeToMonitor(ThreadContext *tc) const override; 529 bool routeToHyp(ThreadContext *tc) const override; 530 bool abortDisable(ThreadContext *tc) override; 531 bool fiqDisable(ThreadContext *tc) override; 532}; 533 534class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 535{ 536 public: 537 VirtualFastInterrupt(); 538}; 539 540/// PC alignment fault (AArch64 only) 541class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 542{ 543 protected: 544 /// The unaligned value of the PC 545 Addr faultPC; 546 public: 547 PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 548 {} 549 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 550 StaticInst::nullStaticInstPtr) override; 551 bool routeToHyp(ThreadContext *tc) const override; 552}; 553 554/// Stack pointer alignment fault (AArch64 only) 555class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 556{ 557 public: 558 SPAlignmentFault(); 559}; 560 561/// System error (AArch64 only) 562class SystemError : public ArmFaultVals<SystemError> 563{ 564 public: 565 SystemError(); 566 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 567 StaticInst::nullStaticInstPtr) override; 568 bool routeToMonitor(ThreadContext *tc) const override; 569 bool routeToHyp(ThreadContext *tc) const override; 570}; 571 572/// System error (AArch64 only) 573class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint> 574{ 575 public: 576 SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss); 577 578 bool routeToHyp(ThreadContext *tc) const override; 579 ExceptionClass ec(ThreadContext *tc) const override; 580}; 581 582// A fault that flushes the pipe, excluding the faulting instructions 583class ArmSev : public ArmFaultVals<ArmSev> 584{ 585 public: 586 ArmSev () {} 587 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 588 StaticInst::nullStaticInstPtr) override; 589}; 590 591/// Illegal Instruction Set State fault (AArch64 only) 592class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 593{ 594 public: 595 IllegalInstSetStateFault(); 596}; 597 598/* 599 * Explicitly declare template static member variables to avoid warnings 600 * in some clang versions 601 */ 602template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals; 603template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals; 604template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals; 605template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals; 606template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals; 607template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals; 608template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals; 609template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals; 610template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals; 611template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals; 612template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals; 613template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals; 614template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals; 615template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals; 616template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals; 617template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals; 618template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals; 619template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals; 620template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals; 621template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals; 622template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals; 623 624 625} // namespace ArmISA 626 627#endif // __ARM_FAULTS_HH__ 628