faults.hh revision 12569:fe1ff4059715 
1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 *          Giacomo Gabrielli
44 *          Thomas Grocutt
45 */
46
47#ifndef __ARM_FAULTS_HH__
48#define __ARM_FAULTS_HH__
49
50#include "arch/arm/miscregs.hh"
51#include "arch/arm/pagetable.hh"
52#include "arch/arm/types.hh"
53#include "base/logging.hh"
54#include "sim/faults.hh"
55#include "sim/full_system.hh"
56
57// The design of the "name" and "vect" functions is in sim/faults.hh
58
59namespace ArmISA
60{
61typedef Addr FaultOffset;
62
63class ArmFault : public FaultBase
64{
65  protected:
66    ExtMachInst machInst;
67    uint32_t issRaw;
68
69    // Helper variables for ARMv8 exception handling
70    bool from64;  // True if the exception is generated from the AArch64 state
71    bool to64;  // True if the exception is taken in AArch64 state
72    ExceptionLevel fromEL;  // Source exception level
73    ExceptionLevel toEL;  // Target exception level
74    OperatingMode fromMode;  // Source operating mode (aarch32)
75    OperatingMode toMode;  // Next operating mode (aarch32)
76
77    // This variable is true if the above fault specific informations
78    // have been updated. This is to prevent that a client is using their
79    // un-updated default constructed value.
80    bool faultUpdated;
81
82    bool hypRouted; // True if the fault has been routed to Hypervisor
83
84    Addr getVector(ThreadContext *tc);
85    Addr getVector64(ThreadContext *tc);
86
87  public:
88    /// Generic fault source enums used to index into
89    /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
90    /// on the current register width state and the translation table format in
91    /// use
92    enum FaultSource
93    {
94        AlignmentFault = 0,
95        InstructionCacheMaintenance,  // Short-desc. format only
96        SynchExtAbtOnTranslTableWalkLL,
97        SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
98        TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
99        AccessFlagLL = TranslationLL + 4,
100        DomainLL = AccessFlagLL + 4,
101        PermissionLL = DomainLL + 4,
102        DebugEvent = PermissionLL + 4,
103        SynchronousExternalAbort,
104        TLBConflictAbort,  // Requires LPAE
105        SynchPtyErrOnMemoryAccess,
106        AsynchronousExternalAbort,
107        AsynchPtyErrOnMemoryAccess,
108        AddressSizeLL,  // AArch64 only
109
110        // Not real faults. These are faults to allow the translation function
111        // to inform the memory access function not to proceed for a prefetch
112        // that misses in the TLB or that targets an uncacheable address
113        PrefetchTLBMiss = AddressSizeLL + 4,
114        PrefetchUncacheable,
115
116        NumFaultSources,
117        FaultSourceInvalid = 0xff
118    };
119
120    /// Encodings of the fault sources when the short-desc. translation table
121    /// format is in use (ARM ARM Issue C B3.13.3)
122    static uint8_t shortDescFaultSources[NumFaultSources];
123    /// Encodings of the fault sources when the long-desc. translation table
124    /// format is in use (ARM ARM Issue C B3.13.3)
125    static uint8_t longDescFaultSources[NumFaultSources];
126    /// Encodings of the fault sources in AArch64 state
127    static uint8_t aarch64FaultSources[NumFaultSources];
128
129    enum AnnotationIDs
130    {
131        S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
132        OVA,   // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
133        SAS,   // DataAbort: Syndrome Access Size
134        SSE,   // DataAbort: Syndrome Sign Extend
135        SRT,   // DataAbort: Syndrome Register Transfer
136
137        // AArch64 only
138        SF,    // DataAbort: width of the accessed register is SixtyFour
139        AR     // DataAbort: Acquire/Release semantics
140    };
141
142    enum TranMethod
143    {
144        LpaeTran,
145        VmsaTran,
146        UnknownTran
147    };
148
149    struct FaultVals
150    {
151        const FaultName name;
152
153        const FaultOffset offset;
154
155        // Offsets used for exceptions taken in AArch64 state
156        const uint16_t currELTOffset;
157        const uint16_t currELHOffset;
158        const uint16_t lowerEL64Offset;
159        const uint16_t lowerEL32Offset;
160
161        const OperatingMode nextMode;
162
163        const uint8_t armPcOffset;
164        const uint8_t thumbPcOffset;
165        // The following two values are used in place of armPcOffset and
166        // thumbPcOffset when the exception return address is saved into ELR
167        // registers (exceptions taken in HYP mode or in AArch64 state)
168        const uint8_t armPcElrOffset;
169        const uint8_t thumbPcElrOffset;
170
171        const bool hypTrappable;
172        const bool abortDisable;
173        const bool fiqDisable;
174
175        // Exception class used to appropriately set the syndrome register
176        // (exceptions taken in HYP mode or in AArch64 state)
177        const ExceptionClass ec;
178
179        FaultStat count;
180        FaultVals(const FaultName& name_, const FaultOffset& offset_,
181                const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
182                const uint16_t& lowerEL64Offset_,
183                const uint16_t& lowerEL32Offset_,
184                const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
185                const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
186                const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
187                const bool& abortDisable_, const bool& fiqDisable_,
188                const ExceptionClass& ec_)
189        : name(name_), offset(offset_), currELTOffset(currELTOffset_),
190          currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
191          lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
192          armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
193          armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
194          hypTrappable(hypTrappable_), abortDisable(abortDisable_),
195          fiqDisable(fiqDisable_), ec(ec_) {}
196    };
197
198    ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
199        machInst(_machInst), issRaw(_iss), from64(false), to64(false),
200        fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED),
201        faultUpdated(false), hypRouted(false) {}
202
203    // Returns the actual syndrome register to use based on the target
204    // exception level
205    MiscRegIndex getSyndromeReg64() const;
206    // Returns the actual fault address register to use based on the target
207    // exception level
208    MiscRegIndex getFaultAddrReg64() const;
209
210    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
211                StaticInst::nullStaticInstPtr) override;
212    void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
213                  StaticInst::nullStaticInstPtr);
214    void update(ThreadContext *tc);
215    virtual void annotate(AnnotationIDs id, uint64_t val) {}
216    virtual FaultStat& countStat() = 0;
217    virtual FaultOffset offset(ThreadContext *tc) = 0;
218    virtual FaultOffset offset64(ThreadContext *tc) = 0;
219    virtual OperatingMode nextMode() = 0;
220    virtual bool routeToMonitor(ThreadContext *tc) const = 0;
221    virtual bool routeToHyp(ThreadContext *tc) const { return false; }
222    virtual uint8_t armPcOffset(bool isHyp) = 0;
223    virtual uint8_t thumbPcOffset(bool isHyp) = 0;
224    virtual uint8_t armPcElrOffset() = 0;
225    virtual uint8_t thumbPcElrOffset() = 0;
226    virtual bool abortDisable(ThreadContext *tc) = 0;
227    virtual bool fiqDisable(ThreadContext *tc) = 0;
228    virtual ExceptionClass ec(ThreadContext *tc) const = 0;
229    virtual uint32_t iss() const = 0;
230    virtual bool isStage2() const { return false; }
231    virtual FSR getFsr(ThreadContext *tc) { return 0; }
232    virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
233};
234
235template<typename T>
236class ArmFaultVals : public ArmFault
237{
238  protected:
239    static FaultVals vals;
240
241  public:
242    ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
243        ArmFault(_machInst, _iss) {}
244    FaultName name() const override { return vals.name; }
245    FaultStat & countStat() override { return vals.count; }
246    FaultOffset offset(ThreadContext *tc) override;
247
248    FaultOffset offset64(ThreadContext *tc) override;
249
250    OperatingMode nextMode() override { return vals.nextMode; }
251    virtual bool routeToMonitor(ThreadContext *tc) const override {
252        return false;
253    }
254    uint8_t armPcOffset(bool isHyp) override {
255        return isHyp ? vals.armPcElrOffset
256                     : vals.armPcOffset;
257    }
258    uint8_t thumbPcOffset(bool isHyp) override {
259        return isHyp ? vals.thumbPcElrOffset
260                     : vals.thumbPcOffset;
261    }
262    uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
263    uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
264    bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
265    bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
266    ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
267    uint32_t iss() const override { return issRaw; }
268};
269
270class Reset : public ArmFaultVals<Reset>
271{
272  public:
273    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
274                StaticInst::nullStaticInstPtr) override;
275};
276
277class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
278{
279  protected:
280    bool unknown;
281    bool disabled;
282    ExceptionClass overrideEc;
283    const char *mnemonic;
284
285  public:
286    UndefinedInstruction(ExtMachInst _machInst,
287                         bool _unknown,
288                         const char *_mnemonic = NULL,
289                         bool _disabled = false) :
290        ArmFaultVals<UndefinedInstruction>(_machInst),
291        unknown(_unknown), disabled(_disabled),
292        overrideEc(EC_INVALID), mnemonic(_mnemonic)
293    {}
294    UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
295            ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
296        ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
297        unknown(false), disabled(true), overrideEc(_overrideEc),
298        mnemonic(_mnemonic)
299    {}
300
301    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
302                StaticInst::nullStaticInstPtr) override;
303    bool routeToHyp(ThreadContext *tc) const override;
304    ExceptionClass ec(ThreadContext *tc) const override;
305    uint32_t iss() const override;
306};
307
308class SupervisorCall : public ArmFaultVals<SupervisorCall>
309{
310  protected:
311    ExceptionClass overrideEc;
312  public:
313    SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
314                   ExceptionClass _overrideEc = EC_INVALID) :
315        ArmFaultVals<SupervisorCall>(_machInst, _iss),
316        overrideEc(_overrideEc)
317    {}
318
319    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
320                StaticInst::nullStaticInstPtr) override;
321    bool routeToHyp(ThreadContext *tc) const override;
322    ExceptionClass ec(ThreadContext *tc) const override;
323    uint32_t iss() const override;
324};
325
326class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
327{
328  public:
329    SecureMonitorCall(ExtMachInst _machInst) :
330        ArmFaultVals<SecureMonitorCall>(_machInst)
331    {}
332
333    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
334                StaticInst::nullStaticInstPtr) override;
335    ExceptionClass ec(ThreadContext *tc) const override;
336    uint32_t iss() const override;
337};
338
339class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
340{
341  protected:
342    ExtMachInst machInst;
343    ExceptionClass overrideEc;
344
345  public:
346    SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
347                   ExceptionClass _overrideEc = EC_INVALID) :
348        ArmFaultVals<SupervisorTrap>(_machInst, _iss),
349        overrideEc(_overrideEc)
350    {}
351
352    bool routeToHyp(ThreadContext *tc) const override;
353    uint32_t iss() const override;
354    ExceptionClass ec(ThreadContext *tc) const override;
355};
356
357class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
358{
359 protected:
360    ExtMachInst machInst;
361    ExceptionClass overrideEc;
362
363  public:
364    SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
365                      ExceptionClass _overrideEc = EC_INVALID) :
366        ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
367        overrideEc(_overrideEc)
368    {}
369
370    ExceptionClass ec(ThreadContext *tc) const override;
371};
372
373class HypervisorCall : public ArmFaultVals<HypervisorCall>
374{
375  public:
376    HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
377
378    ExceptionClass ec(ThreadContext *tc) const override;
379};
380
381class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
382{
383  protected:
384    ExtMachInst machInst;
385    ExceptionClass overrideEc;
386
387  public:
388    HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
389                   ExceptionClass _overrideEc = EC_INVALID) :
390      ArmFaultVals<HypervisorTrap>(_machInst, _iss),
391      overrideEc(_overrideEc)
392    {}
393
394    ExceptionClass ec(ThreadContext *tc) const override;
395};
396
397template <class T>
398class AbortFault : public ArmFaultVals<T>
399{
400  protected:
401    /**
402     * The virtual address the fault occured at. If 2 stages of
403     * translation are being used then this is the intermediate
404     * physical address that is the starting point for the second
405     * stage of translation.
406     */
407    Addr faultAddr;
408    /**
409     * Original virtual address. If the fault was generated on the
410     * second stage of translation then this variable stores the
411     * virtual address used in the original stage 1 translation.
412     */
413    Addr OVAddr;
414    bool write;
415    TlbEntry::DomainType domain;
416    uint8_t source;
417    uint8_t srcEncoded;
418    bool stage2;
419    bool s1ptw;
420    ArmFault::TranMethod tranMethod;
421
422  public:
423    AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
424               uint8_t _source, bool _stage2,
425               ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
426        faultAddr(_faultAddr), OVAddr(0), write(_write),
427        domain(_domain), source(_source), srcEncoded(0),
428        stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
429    {}
430
431    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
432                StaticInst::nullStaticInstPtr) override;
433
434    FSR getFsr(ThreadContext *tc) override;
435    bool abortDisable(ThreadContext *tc) override;
436    uint32_t iss() const override;
437    bool isStage2() const override { return stage2; }
438    void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
439    bool isMMUFault() const;
440};
441
442class PrefetchAbort : public AbortFault<PrefetchAbort>
443{
444  public:
445    static const MiscRegIndex FsrIndex  = MISCREG_IFSR;
446    static const MiscRegIndex FarIndex  = MISCREG_IFAR;
447    static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
448
449    PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
450                  ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
451        AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
452                _source, _stage2, _tranMethod)
453    {}
454
455    ExceptionClass ec(ThreadContext *tc) const override;
456    // @todo: external aborts should be routed if SCR.EA == 1
457    bool routeToMonitor(ThreadContext *tc) const override;
458    bool routeToHyp(ThreadContext *tc) const override;
459};
460
461class DataAbort : public AbortFault<DataAbort>
462{
463  public:
464    static const MiscRegIndex FsrIndex  = MISCREG_DFSR;
465    static const MiscRegIndex FarIndex  = MISCREG_DFAR;
466    static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
467    bool    isv;
468    uint8_t sas;
469    uint8_t sse;
470    uint8_t srt;
471
472    // AArch64 only
473    bool sf;
474    bool ar;
475
476    DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
477              bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
478        AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
479                              _tranMethod),
480        isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
481    {}
482
483    ExceptionClass ec(ThreadContext *tc) const override;
484    // @todo: external aborts should be routed if SCR.EA == 1
485    bool routeToMonitor(ThreadContext *tc) const override;
486    bool routeToHyp(ThreadContext *tc) const override;
487    uint32_t iss() const override;
488    void annotate(AnnotationIDs id, uint64_t val) override;
489};
490
491class VirtualDataAbort : public AbortFault<VirtualDataAbort>
492{
493  public:
494    static const MiscRegIndex FsrIndex  = MISCREG_DFSR;
495    static const MiscRegIndex FarIndex  = MISCREG_DFAR;
496    static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
497
498    VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
499                     uint8_t _source) :
500        AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
501    {}
502
503    void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
504};
505
506class Interrupt : public ArmFaultVals<Interrupt>
507{
508  public:
509    bool routeToMonitor(ThreadContext *tc) const override;
510    bool routeToHyp(ThreadContext *tc) const override;
511    bool abortDisable(ThreadContext *tc) override;
512};
513
514class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
515{
516  public:
517    VirtualInterrupt();
518};
519
520class FastInterrupt : public ArmFaultVals<FastInterrupt>
521{
522  public:
523    bool routeToMonitor(ThreadContext *tc) const override;
524    bool routeToHyp(ThreadContext *tc) const override;
525    bool abortDisable(ThreadContext *tc) override;
526    bool fiqDisable(ThreadContext *tc) override;
527};
528
529class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
530{
531  public:
532    VirtualFastInterrupt();
533};
534
535/// PC alignment fault (AArch64 only)
536class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
537{
538  protected:
539    /// The unaligned value of the PC
540    Addr faultPC;
541  public:
542    PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
543    {}
544    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
545                StaticInst::nullStaticInstPtr) override;
546    bool routeToHyp(ThreadContext *tc) const override;
547};
548
549/// Stack pointer alignment fault (AArch64 only)
550class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
551{
552  public:
553    SPAlignmentFault();
554};
555
556/// System error (AArch64 only)
557class SystemError : public ArmFaultVals<SystemError>
558{
559  public:
560    SystemError();
561    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
562                StaticInst::nullStaticInstPtr) override;
563    bool routeToMonitor(ThreadContext *tc) const override;
564    bool routeToHyp(ThreadContext *tc) const override;
565};
566
567/// System error (AArch64 only)
568class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
569{
570  public:
571    SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
572
573    bool routeToHyp(ThreadContext *tc) const override;
574};
575
576// A fault that flushes the pipe, excluding the faulting instructions
577class ArmSev : public ArmFaultVals<ArmSev>
578{
579  public:
580    ArmSev () {}
581    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
582                StaticInst::nullStaticInstPtr) override;
583};
584
585/// Illegal Instruction Set State fault (AArch64 only)
586class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
587{
588  public:
589    IllegalInstSetStateFault();
590};
591
592/*
593 * Explicitly declare template static member variables to avoid warnings
594 * in some clang versions
595 */
596template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals;
597template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals;
598template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals;
599template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals;
600template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals;
601template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals;
602template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals;
603template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals;
604template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals;
605template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals;
606template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals;
607template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals;
608template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals;
609template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals;
610template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals;
611template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals;
612template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals;
613template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals;
614template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals;
615template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals;
616
617
618} // namespace ArmISA
619
620#endif // __ARM_FAULTS_HH__
621