faults.hh revision 13896
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 37189Sgblack@eecs.umich.edu * All rights reserved 47189Sgblack@eecs.umich.edu * 57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97189Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137189Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 486019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 496019Shines@cs.fsu.edu 507362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5110037SARM gem5 Developers#include "arch/arm/pagetable.hh" 526735Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 5312334Sgabeblack@google.com#include "base/logging.hh" 546019Shines@cs.fsu.edu#include "sim/faults.hh" 558782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 6111294Sandreas.hansson@arm.comtypedef Addr FaultOffset; 626019Shines@cs.fsu.edu 6313896Sgiacomo.travaglini@arm.comclass ArmStaticInst; 6413896Sgiacomo.travaglini@arm.com 657362Sgblack@eecs.umich.educlass ArmFault : public FaultBase 666019Shines@cs.fsu.edu{ 676019Shines@cs.fsu.edu protected: 6810037SARM gem5 Developers ExtMachInst machInst; 6910037SARM gem5 Developers uint32_t issRaw; 7010037SARM gem5 Developers 7110037SARM gem5 Developers // Helper variables for ARMv8 exception handling 7210037SARM gem5 Developers bool from64; // True if the exception is generated from the AArch64 state 7310037SARM gem5 Developers bool to64; // True if the exception is taken in AArch64 state 7410037SARM gem5 Developers ExceptionLevel fromEL; // Source exception level 7510037SARM gem5 Developers ExceptionLevel toEL; // Target exception level 7612569Sgiacomo.travaglini@arm.com OperatingMode fromMode; // Source operating mode (aarch32) 7712569Sgiacomo.travaglini@arm.com OperatingMode toMode; // Next operating mode (aarch32) 7812569Sgiacomo.travaglini@arm.com 7912569Sgiacomo.travaglini@arm.com // This variable is true if the above fault specific informations 8012569Sgiacomo.travaglini@arm.com // have been updated. This is to prevent that a client is using their 8112569Sgiacomo.travaglini@arm.com // un-updated default constructed value. 8212569Sgiacomo.travaglini@arm.com bool faultUpdated; 8310037SARM gem5 Developers 8412402Sgiacomo.travaglini@arm.com bool hypRouted; // True if the fault has been routed to Hypervisor 8512402Sgiacomo.travaglini@arm.com 8613396Sgiacomo.travaglini@arm.com virtual Addr getVector(ThreadContext *tc); 8710037SARM gem5 Developers Addr getVector64(ThreadContext *tc); 886735Sgblack@eecs.umich.edu 896019Shines@cs.fsu.edu public: 9010037SARM gem5 Developers /// Generic fault source enums used to index into 9110037SARM gem5 Developers /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 9210037SARM gem5 Developers /// on the current register width state and the translation table format in 9310037SARM gem5 Developers /// use 9410037SARM gem5 Developers enum FaultSource 957362Sgblack@eecs.umich.edu { 9610037SARM gem5 Developers AlignmentFault = 0, 9710037SARM gem5 Developers InstructionCacheMaintenance, // Short-desc. format only 9810037SARM gem5 Developers SynchExtAbtOnTranslTableWalkLL, 9910037SARM gem5 Developers SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 10010037SARM gem5 Developers TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 10110037SARM gem5 Developers AccessFlagLL = TranslationLL + 4, 10210037SARM gem5 Developers DomainLL = AccessFlagLL + 4, 10310037SARM gem5 Developers PermissionLL = DomainLL + 4, 10410037SARM gem5 Developers DebugEvent = PermissionLL + 4, 10510037SARM gem5 Developers SynchronousExternalAbort, 10610037SARM gem5 Developers TLBConflictAbort, // Requires LPAE 10710037SARM gem5 Developers SynchPtyErrOnMemoryAccess, 10810037SARM gem5 Developers AsynchronousExternalAbort, 10910037SARM gem5 Developers AsynchPtyErrOnMemoryAccess, 11010037SARM gem5 Developers AddressSizeLL, // AArch64 only 1117611SGene.Wu@arm.com 11210037SARM gem5 Developers // Not real faults. These are faults to allow the translation function 11310037SARM gem5 Developers // to inform the memory access function not to proceed for a prefetch 11410037SARM gem5 Developers // that misses in the TLB or that targets an uncacheable address 11510037SARM gem5 Developers PrefetchTLBMiss = AddressSizeLL + 4, 11610037SARM gem5 Developers PrefetchUncacheable, 11710037SARM gem5 Developers 11810037SARM gem5 Developers NumFaultSources, 11910037SARM gem5 Developers FaultSourceInvalid = 0xff 12010037SARM gem5 Developers }; 12110037SARM gem5 Developers 12210037SARM gem5 Developers /// Encodings of the fault sources when the short-desc. translation table 12310037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 12410037SARM gem5 Developers static uint8_t shortDescFaultSources[NumFaultSources]; 12510037SARM gem5 Developers /// Encodings of the fault sources when the long-desc. translation table 12610037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 12710037SARM gem5 Developers static uint8_t longDescFaultSources[NumFaultSources]; 12810037SARM gem5 Developers /// Encodings of the fault sources in AArch64 state 12910037SARM gem5 Developers static uint8_t aarch64FaultSources[NumFaultSources]; 13010037SARM gem5 Developers 13110037SARM gem5 Developers enum AnnotationIDs 13210037SARM gem5 Developers { 13310037SARM gem5 Developers S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 13410037SARM gem5 Developers OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 13510037SARM gem5 Developers SAS, // DataAbort: Syndrome Access Size 13610037SARM gem5 Developers SSE, // DataAbort: Syndrome Sign Extend 13710037SARM gem5 Developers SRT, // DataAbort: Syndrome Register Transfer 13810037SARM gem5 Developers 13910037SARM gem5 Developers // AArch64 only 14010037SARM gem5 Developers SF, // DataAbort: width of the accessed register is SixtyFour 14110037SARM gem5 Developers AR // DataAbort: Acquire/Release semantics 14210037SARM gem5 Developers }; 14310037SARM gem5 Developers 14410037SARM gem5 Developers enum TranMethod 14510037SARM gem5 Developers { 14610037SARM gem5 Developers LpaeTran, 14710037SARM gem5 Developers VmsaTran, 14810037SARM gem5 Developers UnknownTran 1497362Sgblack@eecs.umich.edu }; 1507362Sgblack@eecs.umich.edu 1516735Sgblack@eecs.umich.edu struct FaultVals 1526735Sgblack@eecs.umich.edu { 1536735Sgblack@eecs.umich.edu const FaultName name; 15410037SARM gem5 Developers 1556735Sgblack@eecs.umich.edu const FaultOffset offset; 15610037SARM gem5 Developers 15710037SARM gem5 Developers // Offsets used for exceptions taken in AArch64 state 15810037SARM gem5 Developers const uint16_t currELTOffset; 15910037SARM gem5 Developers const uint16_t currELHOffset; 16010037SARM gem5 Developers const uint16_t lowerEL64Offset; 16110037SARM gem5 Developers const uint16_t lowerEL32Offset; 16210037SARM gem5 Developers 1636735Sgblack@eecs.umich.edu const OperatingMode nextMode; 16410037SARM gem5 Developers 1656735Sgblack@eecs.umich.edu const uint8_t armPcOffset; 1666735Sgblack@eecs.umich.edu const uint8_t thumbPcOffset; 16710037SARM gem5 Developers // The following two values are used in place of armPcOffset and 16810037SARM gem5 Developers // thumbPcOffset when the exception return address is saved into ELR 16910037SARM gem5 Developers // registers (exceptions taken in HYP mode or in AArch64 state) 17010037SARM gem5 Developers const uint8_t armPcElrOffset; 17110037SARM gem5 Developers const uint8_t thumbPcElrOffset; 17210037SARM gem5 Developers 17310037SARM gem5 Developers const bool hypTrappable; 1746735Sgblack@eecs.umich.edu const bool abortDisable; 1756735Sgblack@eecs.umich.edu const bool fiqDisable; 17610037SARM gem5 Developers 17710037SARM gem5 Developers // Exception class used to appropriately set the syndrome register 17810037SARM gem5 Developers // (exceptions taken in HYP mode or in AArch64 state) 17910037SARM gem5 Developers const ExceptionClass ec; 18010037SARM gem5 Developers 1816735Sgblack@eecs.umich.edu FaultStat count; 18212517Srekai.gonzalezalberquilla@arm.com FaultVals(const FaultName& name_, const FaultOffset& offset_, 18312517Srekai.gonzalezalberquilla@arm.com const uint16_t& currELTOffset_, const uint16_t& currELHOffset_, 18412517Srekai.gonzalezalberquilla@arm.com const uint16_t& lowerEL64Offset_, 18512517Srekai.gonzalezalberquilla@arm.com const uint16_t& lowerEL32Offset_, 18612517Srekai.gonzalezalberquilla@arm.com const OperatingMode& nextMode_, const uint8_t& armPcOffset_, 18712517Srekai.gonzalezalberquilla@arm.com const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_, 18812517Srekai.gonzalezalberquilla@arm.com const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_, 18912517Srekai.gonzalezalberquilla@arm.com const bool& abortDisable_, const bool& fiqDisable_, 19012517Srekai.gonzalezalberquilla@arm.com const ExceptionClass& ec_) 19112517Srekai.gonzalezalberquilla@arm.com : name(name_), offset(offset_), currELTOffset(currELTOffset_), 19212517Srekai.gonzalezalberquilla@arm.com currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_), 19312517Srekai.gonzalezalberquilla@arm.com lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_), 19412517Srekai.gonzalezalberquilla@arm.com armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_), 19512517Srekai.gonzalezalberquilla@arm.com armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_), 19612517Srekai.gonzalezalberquilla@arm.com hypTrappable(hypTrappable_), abortDisable(abortDisable_), 19712517Srekai.gonzalezalberquilla@arm.com fiqDisable(fiqDisable_), ec(ec_) {} 1986735Sgblack@eecs.umich.edu }; 1996735Sgblack@eecs.umich.edu 20010037SARM gem5 Developers ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 20110537Sandreas.hansson@arm.com machInst(_machInst), issRaw(_iss), from64(false), to64(false), 20212569Sgiacomo.travaglini@arm.com fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), 20312569Sgiacomo.travaglini@arm.com faultUpdated(false), hypRouted(false) {} 20410037SARM gem5 Developers 20510037SARM gem5 Developers // Returns the actual syndrome register to use based on the target 20610037SARM gem5 Developers // exception level 20710037SARM gem5 Developers MiscRegIndex getSyndromeReg64() const; 20810037SARM gem5 Developers // Returns the actual fault address register to use based on the target 20910037SARM gem5 Developers // exception level 21010037SARM gem5 Developers MiscRegIndex getFaultAddrReg64() const; 21110037SARM gem5 Developers 21210417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 21312176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 21410417Sandreas.hansson@arm.com void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 21510417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 21612569Sgiacomo.travaglini@arm.com void update(ThreadContext *tc); 21713896Sgiacomo.travaglini@arm.com 21813896Sgiacomo.travaglini@arm.com ArmStaticInst *instrAnnotate(const StaticInstPtr &inst); 21910037SARM gem5 Developers virtual void annotate(AnnotationIDs id, uint64_t val) {} 2206735Sgblack@eecs.umich.edu virtual FaultStat& countStat() = 0; 22110037SARM gem5 Developers virtual FaultOffset offset(ThreadContext *tc) = 0; 22212511Schuan.zhu@arm.com virtual FaultOffset offset64(ThreadContext *tc) = 0; 2236735Sgblack@eecs.umich.edu virtual OperatingMode nextMode() = 0; 22410037SARM gem5 Developers virtual bool routeToMonitor(ThreadContext *tc) const = 0; 22510037SARM gem5 Developers virtual bool routeToHyp(ThreadContext *tc) const { return false; } 22610037SARM gem5 Developers virtual uint8_t armPcOffset(bool isHyp) = 0; 22710037SARM gem5 Developers virtual uint8_t thumbPcOffset(bool isHyp) = 0; 22810037SARM gem5 Developers virtual uint8_t armPcElrOffset() = 0; 22910037SARM gem5 Developers virtual uint8_t thumbPcElrOffset() = 0; 23010037SARM gem5 Developers virtual bool abortDisable(ThreadContext *tc) = 0; 23110037SARM gem5 Developers virtual bool fiqDisable(ThreadContext *tc) = 0; 23210037SARM gem5 Developers virtual ExceptionClass ec(ThreadContext *tc) const = 0; 23310037SARM gem5 Developers virtual uint32_t iss() const = 0; 23410037SARM gem5 Developers virtual bool isStage2() const { return false; } 23512570Sgiacomo.travaglini@arm.com virtual FSR getFsr(ThreadContext *tc) const { return 0; } 23610037SARM gem5 Developers virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 2376019Shines@cs.fsu.edu}; 2386019Shines@cs.fsu.edu 2396735Sgblack@eecs.umich.edutemplate<typename T> 2407362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault 2416019Shines@cs.fsu.edu{ 2426735Sgblack@eecs.umich.edu protected: 2436735Sgblack@eecs.umich.edu static FaultVals vals; 2446735Sgblack@eecs.umich.edu 2456019Shines@cs.fsu.edu public: 24610037SARM gem5 Developers ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 24710037SARM gem5 Developers ArmFault(_machInst, _iss) {} 24812176Sandreas.sandberg@arm.com FaultName name() const override { return vals.name; } 24912176Sandreas.sandberg@arm.com FaultStat & countStat() override { return vals.count; } 25012176Sandreas.sandberg@arm.com FaultOffset offset(ThreadContext *tc) override; 25110037SARM gem5 Developers 25212511Schuan.zhu@arm.com FaultOffset offset64(ThreadContext *tc) override; 25310037SARM gem5 Developers 25412176Sandreas.sandberg@arm.com OperatingMode nextMode() override { return vals.nextMode; } 25512176Sandreas.sandberg@arm.com virtual bool routeToMonitor(ThreadContext *tc) const override { 25612176Sandreas.sandberg@arm.com return false; 25712176Sandreas.sandberg@arm.com } 25812176Sandreas.sandberg@arm.com uint8_t armPcOffset(bool isHyp) override { 25912176Sandreas.sandberg@arm.com return isHyp ? vals.armPcElrOffset 26012176Sandreas.sandberg@arm.com : vals.armPcOffset; 26112176Sandreas.sandberg@arm.com } 26212176Sandreas.sandberg@arm.com uint8_t thumbPcOffset(bool isHyp) override { 26312176Sandreas.sandberg@arm.com return isHyp ? vals.thumbPcElrOffset 26412176Sandreas.sandberg@arm.com : vals.thumbPcOffset; 26512176Sandreas.sandberg@arm.com } 26612176Sandreas.sandberg@arm.com uint8_t armPcElrOffset() override { return vals.armPcElrOffset; } 26712176Sandreas.sandberg@arm.com uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; } 26812176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; } 26912176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; } 27012176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; } 27112176Sandreas.sandberg@arm.com uint32_t iss() const override { return issRaw; } 2726019Shines@cs.fsu.edu}; 2736019Shines@cs.fsu.edu 2747400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset> 2757400SAli.Saidi@ARM.com{ 27613396Sgiacomo.travaglini@arm.com protected: 27713396Sgiacomo.travaglini@arm.com Addr getVector(ThreadContext *tc) override; 27813396Sgiacomo.travaglini@arm.com 2797400SAli.Saidi@ARM.com public: 28010417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 28112176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 2827400SAli.Saidi@ARM.com}; 2837189Sgblack@eecs.umich.edu 2847362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 2857189Sgblack@eecs.umich.edu{ 2867189Sgblack@eecs.umich.edu protected: 2877189Sgblack@eecs.umich.edu bool unknown; 2887640Sgblack@eecs.umich.edu bool disabled; 28910037SARM gem5 Developers ExceptionClass overrideEc; 29010205SAli.Saidi@ARM.com const char *mnemonic; 2917189Sgblack@eecs.umich.edu 2927189Sgblack@eecs.umich.edu public: 2937189Sgblack@eecs.umich.edu UndefinedInstruction(ExtMachInst _machInst, 2947189Sgblack@eecs.umich.edu bool _unknown, 2957640Sgblack@eecs.umich.edu const char *_mnemonic = NULL, 2967640Sgblack@eecs.umich.edu bool _disabled = false) : 29710037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst), 29810205SAli.Saidi@ARM.com unknown(_unknown), disabled(_disabled), 29910205SAli.Saidi@ARM.com overrideEc(EC_INVALID), mnemonic(_mnemonic) 30010037SARM gem5 Developers {} 30110205SAli.Saidi@ARM.com UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 30210205SAli.Saidi@ARM.com ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 30310037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 30410205SAli.Saidi@ARM.com unknown(false), disabled(true), overrideEc(_overrideEc), 30510205SAli.Saidi@ARM.com mnemonic(_mnemonic) 3068782Sgblack@eecs.umich.edu {} 3077189Sgblack@eecs.umich.edu 30810417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 30912176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 31012176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 31112176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 31212176Sandreas.sandberg@arm.com uint32_t iss() const override; 3137189Sgblack@eecs.umich.edu}; 3147189Sgblack@eecs.umich.edu 3157362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall> 3167197Sgblack@eecs.umich.edu{ 3177197Sgblack@eecs.umich.edu protected: 31810037SARM gem5 Developers ExceptionClass overrideEc; 3197197Sgblack@eecs.umich.edu public: 32010037SARM gem5 Developers SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 32110037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 32210037SARM gem5 Developers ArmFaultVals<SupervisorCall>(_machInst, _iss), 32310037SARM gem5 Developers overrideEc(_overrideEc) 3248782Sgblack@eecs.umich.edu {} 3257197Sgblack@eecs.umich.edu 32610417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 32712176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 32812176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 32912176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 33012176Sandreas.sandberg@arm.com uint32_t iss() const override; 33110037SARM gem5 Developers}; 33210037SARM gem5 Developers 33310037SARM gem5 Developersclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 33410037SARM gem5 Developers{ 33510037SARM gem5 Developers public: 33610037SARM gem5 Developers SecureMonitorCall(ExtMachInst _machInst) : 33710037SARM gem5 Developers ArmFaultVals<SecureMonitorCall>(_machInst) 33810037SARM gem5 Developers {} 33910037SARM gem5 Developers 34010417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 34112176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 34212176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 34312176Sandreas.sandberg@arm.com uint32_t iss() const override; 34410037SARM gem5 Developers}; 34510037SARM gem5 Developers 34610037SARM gem5 Developersclass SupervisorTrap : public ArmFaultVals<SupervisorTrap> 34710037SARM gem5 Developers{ 34810037SARM gem5 Developers protected: 34910037SARM gem5 Developers ExtMachInst machInst; 35010037SARM gem5 Developers ExceptionClass overrideEc; 35110037SARM gem5 Developers 35210037SARM gem5 Developers public: 35310037SARM gem5 Developers SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 35410037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 35510037SARM gem5 Developers ArmFaultVals<SupervisorTrap>(_machInst, _iss), 35610037SARM gem5 Developers overrideEc(_overrideEc) 35710037SARM gem5 Developers {} 35810037SARM gem5 Developers 35912509Schuan.zhu@arm.com bool routeToHyp(ThreadContext *tc) const override; 36012509Schuan.zhu@arm.com uint32_t iss() const override; 36112176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 36210037SARM gem5 Developers}; 36310037SARM gem5 Developers 36410037SARM gem5 Developersclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 36510037SARM gem5 Developers{ 36610037SARM gem5 Developers protected: 36710037SARM gem5 Developers ExtMachInst machInst; 36810037SARM gem5 Developers ExceptionClass overrideEc; 36910037SARM gem5 Developers 37010037SARM gem5 Developers public: 37110037SARM gem5 Developers SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 37210037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 37310037SARM gem5 Developers ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 37410037SARM gem5 Developers overrideEc(_overrideEc) 37510037SARM gem5 Developers {} 37610037SARM gem5 Developers 37712176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 37810037SARM gem5 Developers}; 37910037SARM gem5 Developers 38010037SARM gem5 Developersclass HypervisorCall : public ArmFaultVals<HypervisorCall> 38110037SARM gem5 Developers{ 38210037SARM gem5 Developers public: 38310037SARM gem5 Developers HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 38411576SDylan.Johnson@ARM.com 38512176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 38610037SARM gem5 Developers}; 38710037SARM gem5 Developers 38810037SARM gem5 Developersclass HypervisorTrap : public ArmFaultVals<HypervisorTrap> 38910037SARM gem5 Developers{ 39010037SARM gem5 Developers protected: 39110037SARM gem5 Developers ExtMachInst machInst; 39210037SARM gem5 Developers ExceptionClass overrideEc; 39310037SARM gem5 Developers 39410037SARM gem5 Developers public: 39510037SARM gem5 Developers HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 39610037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 39710037SARM gem5 Developers ArmFaultVals<HypervisorTrap>(_machInst, _iss), 39810037SARM gem5 Developers overrideEc(_overrideEc) 39910037SARM gem5 Developers {} 40010037SARM gem5 Developers 40112176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 4027197Sgblack@eecs.umich.edu}; 4037362Sgblack@eecs.umich.edu 4047362Sgblack@eecs.umich.edutemplate <class T> 4057362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T> 4067362Sgblack@eecs.umich.edu{ 4077362Sgblack@eecs.umich.edu protected: 40810037SARM gem5 Developers /** 40910037SARM gem5 Developers * The virtual address the fault occured at. If 2 stages of 41010037SARM gem5 Developers * translation are being used then this is the intermediate 41110037SARM gem5 Developers * physical address that is the starting point for the second 41210037SARM gem5 Developers * stage of translation. 41310037SARM gem5 Developers */ 4147362Sgblack@eecs.umich.edu Addr faultAddr; 41510037SARM gem5 Developers /** 41610037SARM gem5 Developers * Original virtual address. If the fault was generated on the 41710037SARM gem5 Developers * second stage of translation then this variable stores the 41810037SARM gem5 Developers * virtual address used in the original stage 1 translation. 41910037SARM gem5 Developers */ 42010037SARM gem5 Developers Addr OVAddr; 4217362Sgblack@eecs.umich.edu bool write; 42210037SARM gem5 Developers TlbEntry::DomainType domain; 42310037SARM gem5 Developers uint8_t source; 42410037SARM gem5 Developers uint8_t srcEncoded; 42510037SARM gem5 Developers bool stage2; 42610037SARM gem5 Developers bool s1ptw; 42710037SARM gem5 Developers ArmFault::TranMethod tranMethod; 4287362Sgblack@eecs.umich.edu 4297362Sgblack@eecs.umich.edu public: 43010537Sandreas.hansson@arm.com AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, 43110537Sandreas.hansson@arm.com uint8_t _source, bool _stage2, 43210537Sandreas.hansson@arm.com ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 43310537Sandreas.hansson@arm.com faultAddr(_faultAddr), OVAddr(0), write(_write), 43410537Sandreas.hansson@arm.com domain(_domain), source(_source), srcEncoded(0), 43510037SARM gem5 Developers stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 4367362Sgblack@eecs.umich.edu {} 4377362Sgblack@eecs.umich.edu 43810417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 43912176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 44010037SARM gem5 Developers 44112570Sgiacomo.travaglini@arm.com FSR getFsr(ThreadContext *tc) const override; 44212570Sgiacomo.travaglini@arm.com uint8_t getFaultStatusCode(ThreadContext *tc) const; 44312176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 44412176Sandreas.sandberg@arm.com uint32_t iss() const override; 44512176Sandreas.sandberg@arm.com bool isStage2() const override { return stage2; } 44612176Sandreas.sandberg@arm.com void annotate(ArmFault::AnnotationIDs id, uint64_t val) override; 44712570Sgiacomo.travaglini@arm.com void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override; 44810037SARM gem5 Developers bool isMMUFault() const; 4497362Sgblack@eecs.umich.edu}; 4507362Sgblack@eecs.umich.edu 4517362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort> 4527362Sgblack@eecs.umich.edu{ 4537362Sgblack@eecs.umich.edu public: 45410037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_IFSR; 45510037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_IFAR; 45610037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 4577362Sgblack@eecs.umich.edu 45810037SARM gem5 Developers PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 45910037SARM gem5 Developers ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 46010037SARM gem5 Developers AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 46110037SARM gem5 Developers _source, _stage2, _tranMethod) 4627362Sgblack@eecs.umich.edu {} 46310037SARM gem5 Developers 46412176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 46510037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 46612176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 46712176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 4687362Sgblack@eecs.umich.edu}; 4697362Sgblack@eecs.umich.edu 4707362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort> 4717362Sgblack@eecs.umich.edu{ 4727362Sgblack@eecs.umich.edu public: 47310037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 47410037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 47510037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 47610037SARM gem5 Developers bool isv; 47710037SARM gem5 Developers uint8_t sas; 47810037SARM gem5 Developers uint8_t sse; 47910037SARM gem5 Developers uint8_t srt; 4807362Sgblack@eecs.umich.edu 48110037SARM gem5 Developers // AArch64 only 48210037SARM gem5 Developers bool sf; 48310037SARM gem5 Developers bool ar; 48410037SARM gem5 Developers 48510037SARM gem5 Developers DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 48610037SARM gem5 Developers bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 48710037SARM gem5 Developers AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 48810037SARM gem5 Developers _tranMethod), 48910037SARM gem5 Developers isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 4907362Sgblack@eecs.umich.edu {} 49110037SARM gem5 Developers 49212176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 49310037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 49412176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 49512176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 49612176Sandreas.sandberg@arm.com uint32_t iss() const override; 49712176Sandreas.sandberg@arm.com void annotate(AnnotationIDs id, uint64_t val) override; 4987362Sgblack@eecs.umich.edu}; 4997362Sgblack@eecs.umich.edu 50010037SARM gem5 Developersclass VirtualDataAbort : public AbortFault<VirtualDataAbort> 50110037SARM gem5 Developers{ 50210037SARM gem5 Developers public: 50310037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 50410037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 50510037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 50610037SARM gem5 Developers 50710037SARM gem5 Developers VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 50810037SARM gem5 Developers uint8_t _source) : 50910037SARM gem5 Developers AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 51010037SARM gem5 Developers {} 51110037SARM gem5 Developers 51212176Sandreas.sandberg@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 51310037SARM gem5 Developers}; 51410037SARM gem5 Developers 51510037SARM gem5 Developersclass Interrupt : public ArmFaultVals<Interrupt> 51610037SARM gem5 Developers{ 51710037SARM gem5 Developers public: 51812176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 51912176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 52012176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 52110037SARM gem5 Developers}; 52210037SARM gem5 Developers 52310037SARM gem5 Developersclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 52410037SARM gem5 Developers{ 52510037SARM gem5 Developers public: 52610037SARM gem5 Developers VirtualInterrupt(); 52710037SARM gem5 Developers}; 52810037SARM gem5 Developers 52910037SARM gem5 Developersclass FastInterrupt : public ArmFaultVals<FastInterrupt> 53010037SARM gem5 Developers{ 53110037SARM gem5 Developers public: 53212176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 53312176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 53412176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 53512176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext *tc) override; 53610037SARM gem5 Developers}; 53710037SARM gem5 Developers 53810037SARM gem5 Developersclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 53910037SARM gem5 Developers{ 54010037SARM gem5 Developers public: 54110037SARM gem5 Developers VirtualFastInterrupt(); 54210037SARM gem5 Developers}; 54310037SARM gem5 Developers 54410037SARM gem5 Developers/// PC alignment fault (AArch64 only) 54510037SARM gem5 Developersclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 54610037SARM gem5 Developers{ 54710037SARM gem5 Developers protected: 54810037SARM gem5 Developers /// The unaligned value of the PC 54910037SARM gem5 Developers Addr faultPC; 55010037SARM gem5 Developers public: 55110037SARM gem5 Developers PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 55210037SARM gem5 Developers {} 55310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 55412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 55512568Sgiacomo.travaglini@arm.com bool routeToHyp(ThreadContext *tc) const override; 55610037SARM gem5 Developers}; 55710037SARM gem5 Developers 55810037SARM gem5 Developers/// Stack pointer alignment fault (AArch64 only) 55910037SARM gem5 Developersclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 56010037SARM gem5 Developers{ 56110037SARM gem5 Developers public: 56210037SARM gem5 Developers SPAlignmentFault(); 56310037SARM gem5 Developers}; 56410037SARM gem5 Developers 56510037SARM gem5 Developers/// System error (AArch64 only) 56610037SARM gem5 Developersclass SystemError : public ArmFaultVals<SystemError> 56710037SARM gem5 Developers{ 56810037SARM gem5 Developers public: 56910037SARM gem5 Developers SystemError(); 57010417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 57112176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 57212176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 57312176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 57410037SARM gem5 Developers}; 5756019Shines@cs.fsu.edu 57612299Sandreas.sandberg@arm.com/// System error (AArch64 only) 57712299Sandreas.sandberg@arm.comclass SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint> 57812299Sandreas.sandberg@arm.com{ 57912299Sandreas.sandberg@arm.com public: 58012299Sandreas.sandberg@arm.com SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss); 58112299Sandreas.sandberg@arm.com 58212299Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 58312732Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 58412299Sandreas.sandberg@arm.com}; 58512299Sandreas.sandberg@arm.com 5867652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions 5878518Sgeoffrey.blake@arm.comclass ArmSev : public ArmFaultVals<ArmSev> 5888518Sgeoffrey.blake@arm.com{ 5898518Sgeoffrey.blake@arm.com public: 5908518Sgeoffrey.blake@arm.com ArmSev () {} 59110417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 59212176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 5938518Sgeoffrey.blake@arm.com}; 5948518Sgeoffrey.blake@arm.com 59510037SARM gem5 Developers/// Illegal Instruction Set State fault (AArch64 only) 59610037SARM gem5 Developersclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 59710037SARM gem5 Developers{ 59810037SARM gem5 Developers public: 59910037SARM gem5 Developers IllegalInstSetStateFault(); 60010037SARM gem5 Developers}; 60110037SARM gem5 Developers 60211929SMatteo.Andreozzi@arm.com/* 60312032Sandreas.sandberg@arm.com * Explicitly declare template static member variables to avoid warnings 60412032Sandreas.sandberg@arm.com * in some clang versions 60511929SMatteo.Andreozzi@arm.com */ 60611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals; 60711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals; 60811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals; 60911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals; 61011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals; 61111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals; 61211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals; 61311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals; 61411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals; 61511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals; 61611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals; 61711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals; 61811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals; 61913456Snikos.nikoleris@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals; 62011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals; 62111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals; 62211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals; 62311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals; 62411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals; 62512299Sandreas.sandberg@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals; 62611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals; 62711929SMatteo.Andreozzi@arm.com 62811929SMatteo.Andreozzi@arm.com 6297811Ssteve.reinhardt@amd.com} // namespace ArmISA 6306019Shines@cs.fsu.edu 6316019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__ 632