faults.hh revision 12570
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 37189Sgblack@eecs.umich.edu * All rights reserved 47189Sgblack@eecs.umich.edu * 57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97189Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137189Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 486019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 496019Shines@cs.fsu.edu 507362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5110037SARM gem5 Developers#include "arch/arm/pagetable.hh" 526735Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 5312334Sgabeblack@google.com#include "base/logging.hh" 546019Shines@cs.fsu.edu#include "sim/faults.hh" 558782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 6111294Sandreas.hansson@arm.comtypedef Addr FaultOffset; 626019Shines@cs.fsu.edu 637362Sgblack@eecs.umich.educlass ArmFault : public FaultBase 646019Shines@cs.fsu.edu{ 656019Shines@cs.fsu.edu protected: 6610037SARM gem5 Developers ExtMachInst machInst; 6710037SARM gem5 Developers uint32_t issRaw; 6810037SARM gem5 Developers 6910037SARM gem5 Developers // Helper variables for ARMv8 exception handling 7010037SARM gem5 Developers bool from64; // True if the exception is generated from the AArch64 state 7110037SARM gem5 Developers bool to64; // True if the exception is taken in AArch64 state 7210037SARM gem5 Developers ExceptionLevel fromEL; // Source exception level 7310037SARM gem5 Developers ExceptionLevel toEL; // Target exception level 7412569Sgiacomo.travaglini@arm.com OperatingMode fromMode; // Source operating mode (aarch32) 7512569Sgiacomo.travaglini@arm.com OperatingMode toMode; // Next operating mode (aarch32) 7612569Sgiacomo.travaglini@arm.com 7712569Sgiacomo.travaglini@arm.com // This variable is true if the above fault specific informations 7812569Sgiacomo.travaglini@arm.com // have been updated. This is to prevent that a client is using their 7912569Sgiacomo.travaglini@arm.com // un-updated default constructed value. 8012569Sgiacomo.travaglini@arm.com bool faultUpdated; 8110037SARM gem5 Developers 8212402Sgiacomo.travaglini@arm.com bool hypRouted; // True if the fault has been routed to Hypervisor 8312402Sgiacomo.travaglini@arm.com 846735Sgblack@eecs.umich.edu Addr getVector(ThreadContext *tc); 8510037SARM gem5 Developers Addr getVector64(ThreadContext *tc); 866735Sgblack@eecs.umich.edu 876019Shines@cs.fsu.edu public: 8810037SARM gem5 Developers /// Generic fault source enums used to index into 8910037SARM gem5 Developers /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 9010037SARM gem5 Developers /// on the current register width state and the translation table format in 9110037SARM gem5 Developers /// use 9210037SARM gem5 Developers enum FaultSource 937362Sgblack@eecs.umich.edu { 9410037SARM gem5 Developers AlignmentFault = 0, 9510037SARM gem5 Developers InstructionCacheMaintenance, // Short-desc. format only 9610037SARM gem5 Developers SynchExtAbtOnTranslTableWalkLL, 9710037SARM gem5 Developers SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 9810037SARM gem5 Developers TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 9910037SARM gem5 Developers AccessFlagLL = TranslationLL + 4, 10010037SARM gem5 Developers DomainLL = AccessFlagLL + 4, 10110037SARM gem5 Developers PermissionLL = DomainLL + 4, 10210037SARM gem5 Developers DebugEvent = PermissionLL + 4, 10310037SARM gem5 Developers SynchronousExternalAbort, 10410037SARM gem5 Developers TLBConflictAbort, // Requires LPAE 10510037SARM gem5 Developers SynchPtyErrOnMemoryAccess, 10610037SARM gem5 Developers AsynchronousExternalAbort, 10710037SARM gem5 Developers AsynchPtyErrOnMemoryAccess, 10810037SARM gem5 Developers AddressSizeLL, // AArch64 only 1097611SGene.Wu@arm.com 11010037SARM gem5 Developers // Not real faults. These are faults to allow the translation function 11110037SARM gem5 Developers // to inform the memory access function not to proceed for a prefetch 11210037SARM gem5 Developers // that misses in the TLB or that targets an uncacheable address 11310037SARM gem5 Developers PrefetchTLBMiss = AddressSizeLL + 4, 11410037SARM gem5 Developers PrefetchUncacheable, 11510037SARM gem5 Developers 11610037SARM gem5 Developers NumFaultSources, 11710037SARM gem5 Developers FaultSourceInvalid = 0xff 11810037SARM gem5 Developers }; 11910037SARM gem5 Developers 12010037SARM gem5 Developers /// Encodings of the fault sources when the short-desc. translation table 12110037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 12210037SARM gem5 Developers static uint8_t shortDescFaultSources[NumFaultSources]; 12310037SARM gem5 Developers /// Encodings of the fault sources when the long-desc. translation table 12410037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 12510037SARM gem5 Developers static uint8_t longDescFaultSources[NumFaultSources]; 12610037SARM gem5 Developers /// Encodings of the fault sources in AArch64 state 12710037SARM gem5 Developers static uint8_t aarch64FaultSources[NumFaultSources]; 12810037SARM gem5 Developers 12910037SARM gem5 Developers enum AnnotationIDs 13010037SARM gem5 Developers { 13110037SARM gem5 Developers S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 13210037SARM gem5 Developers OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 13310037SARM gem5 Developers SAS, // DataAbort: Syndrome Access Size 13410037SARM gem5 Developers SSE, // DataAbort: Syndrome Sign Extend 13510037SARM gem5 Developers SRT, // DataAbort: Syndrome Register Transfer 13610037SARM gem5 Developers 13710037SARM gem5 Developers // AArch64 only 13810037SARM gem5 Developers SF, // DataAbort: width of the accessed register is SixtyFour 13910037SARM gem5 Developers AR // DataAbort: Acquire/Release semantics 14010037SARM gem5 Developers }; 14110037SARM gem5 Developers 14210037SARM gem5 Developers enum TranMethod 14310037SARM gem5 Developers { 14410037SARM gem5 Developers LpaeTran, 14510037SARM gem5 Developers VmsaTran, 14610037SARM gem5 Developers UnknownTran 1477362Sgblack@eecs.umich.edu }; 1487362Sgblack@eecs.umich.edu 1496735Sgblack@eecs.umich.edu struct FaultVals 1506735Sgblack@eecs.umich.edu { 1516735Sgblack@eecs.umich.edu const FaultName name; 15210037SARM gem5 Developers 1536735Sgblack@eecs.umich.edu const FaultOffset offset; 15410037SARM gem5 Developers 15510037SARM gem5 Developers // Offsets used for exceptions taken in AArch64 state 15610037SARM gem5 Developers const uint16_t currELTOffset; 15710037SARM gem5 Developers const uint16_t currELHOffset; 15810037SARM gem5 Developers const uint16_t lowerEL64Offset; 15910037SARM gem5 Developers const uint16_t lowerEL32Offset; 16010037SARM gem5 Developers 1616735Sgblack@eecs.umich.edu const OperatingMode nextMode; 16210037SARM gem5 Developers 1636735Sgblack@eecs.umich.edu const uint8_t armPcOffset; 1646735Sgblack@eecs.umich.edu const uint8_t thumbPcOffset; 16510037SARM gem5 Developers // The following two values are used in place of armPcOffset and 16610037SARM gem5 Developers // thumbPcOffset when the exception return address is saved into ELR 16710037SARM gem5 Developers // registers (exceptions taken in HYP mode or in AArch64 state) 16810037SARM gem5 Developers const uint8_t armPcElrOffset; 16910037SARM gem5 Developers const uint8_t thumbPcElrOffset; 17010037SARM gem5 Developers 17110037SARM gem5 Developers const bool hypTrappable; 1726735Sgblack@eecs.umich.edu const bool abortDisable; 1736735Sgblack@eecs.umich.edu const bool fiqDisable; 17410037SARM gem5 Developers 17510037SARM gem5 Developers // Exception class used to appropriately set the syndrome register 17610037SARM gem5 Developers // (exceptions taken in HYP mode or in AArch64 state) 17710037SARM gem5 Developers const ExceptionClass ec; 17810037SARM gem5 Developers 1796735Sgblack@eecs.umich.edu FaultStat count; 18012517Srekai.gonzalezalberquilla@arm.com FaultVals(const FaultName& name_, const FaultOffset& offset_, 18112517Srekai.gonzalezalberquilla@arm.com const uint16_t& currELTOffset_, const uint16_t& currELHOffset_, 18212517Srekai.gonzalezalberquilla@arm.com const uint16_t& lowerEL64Offset_, 18312517Srekai.gonzalezalberquilla@arm.com const uint16_t& lowerEL32Offset_, 18412517Srekai.gonzalezalberquilla@arm.com const OperatingMode& nextMode_, const uint8_t& armPcOffset_, 18512517Srekai.gonzalezalberquilla@arm.com const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_, 18612517Srekai.gonzalezalberquilla@arm.com const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_, 18712517Srekai.gonzalezalberquilla@arm.com const bool& abortDisable_, const bool& fiqDisable_, 18812517Srekai.gonzalezalberquilla@arm.com const ExceptionClass& ec_) 18912517Srekai.gonzalezalberquilla@arm.com : name(name_), offset(offset_), currELTOffset(currELTOffset_), 19012517Srekai.gonzalezalberquilla@arm.com currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_), 19112517Srekai.gonzalezalberquilla@arm.com lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_), 19212517Srekai.gonzalezalberquilla@arm.com armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_), 19312517Srekai.gonzalezalberquilla@arm.com armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_), 19412517Srekai.gonzalezalberquilla@arm.com hypTrappable(hypTrappable_), abortDisable(abortDisable_), 19512517Srekai.gonzalezalberquilla@arm.com fiqDisable(fiqDisable_), ec(ec_) {} 1966735Sgblack@eecs.umich.edu }; 1976735Sgblack@eecs.umich.edu 19810037SARM gem5 Developers ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 19910537Sandreas.hansson@arm.com machInst(_machInst), issRaw(_iss), from64(false), to64(false), 20012569Sgiacomo.travaglini@arm.com fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), 20112569Sgiacomo.travaglini@arm.com faultUpdated(false), hypRouted(false) {} 20210037SARM gem5 Developers 20310037SARM gem5 Developers // Returns the actual syndrome register to use based on the target 20410037SARM gem5 Developers // exception level 20510037SARM gem5 Developers MiscRegIndex getSyndromeReg64() const; 20610037SARM gem5 Developers // Returns the actual fault address register to use based on the target 20710037SARM gem5 Developers // exception level 20810037SARM gem5 Developers MiscRegIndex getFaultAddrReg64() const; 20910037SARM gem5 Developers 21010417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 21112176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 21210417Sandreas.hansson@arm.com void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 21310417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 21412569Sgiacomo.travaglini@arm.com void update(ThreadContext *tc); 21510037SARM gem5 Developers virtual void annotate(AnnotationIDs id, uint64_t val) {} 2166735Sgblack@eecs.umich.edu virtual FaultStat& countStat() = 0; 21710037SARM gem5 Developers virtual FaultOffset offset(ThreadContext *tc) = 0; 21812511Schuan.zhu@arm.com virtual FaultOffset offset64(ThreadContext *tc) = 0; 2196735Sgblack@eecs.umich.edu virtual OperatingMode nextMode() = 0; 22010037SARM gem5 Developers virtual bool routeToMonitor(ThreadContext *tc) const = 0; 22110037SARM gem5 Developers virtual bool routeToHyp(ThreadContext *tc) const { return false; } 22210037SARM gem5 Developers virtual uint8_t armPcOffset(bool isHyp) = 0; 22310037SARM gem5 Developers virtual uint8_t thumbPcOffset(bool isHyp) = 0; 22410037SARM gem5 Developers virtual uint8_t armPcElrOffset() = 0; 22510037SARM gem5 Developers virtual uint8_t thumbPcElrOffset() = 0; 22610037SARM gem5 Developers virtual bool abortDisable(ThreadContext *tc) = 0; 22710037SARM gem5 Developers virtual bool fiqDisable(ThreadContext *tc) = 0; 22810037SARM gem5 Developers virtual ExceptionClass ec(ThreadContext *tc) const = 0; 22910037SARM gem5 Developers virtual uint32_t iss() const = 0; 23010037SARM gem5 Developers virtual bool isStage2() const { return false; } 23112570Sgiacomo.travaglini@arm.com virtual FSR getFsr(ThreadContext *tc) const { return 0; } 23210037SARM gem5 Developers virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 2336019Shines@cs.fsu.edu}; 2346019Shines@cs.fsu.edu 2356735Sgblack@eecs.umich.edutemplate<typename T> 2367362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault 2376019Shines@cs.fsu.edu{ 2386735Sgblack@eecs.umich.edu protected: 2396735Sgblack@eecs.umich.edu static FaultVals vals; 2406735Sgblack@eecs.umich.edu 2416019Shines@cs.fsu.edu public: 24210037SARM gem5 Developers ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 24310037SARM gem5 Developers ArmFault(_machInst, _iss) {} 24412176Sandreas.sandberg@arm.com FaultName name() const override { return vals.name; } 24512176Sandreas.sandberg@arm.com FaultStat & countStat() override { return vals.count; } 24612176Sandreas.sandberg@arm.com FaultOffset offset(ThreadContext *tc) override; 24710037SARM gem5 Developers 24812511Schuan.zhu@arm.com FaultOffset offset64(ThreadContext *tc) override; 24910037SARM gem5 Developers 25012176Sandreas.sandberg@arm.com OperatingMode nextMode() override { return vals.nextMode; } 25112176Sandreas.sandberg@arm.com virtual bool routeToMonitor(ThreadContext *tc) const override { 25212176Sandreas.sandberg@arm.com return false; 25312176Sandreas.sandberg@arm.com } 25412176Sandreas.sandberg@arm.com uint8_t armPcOffset(bool isHyp) override { 25512176Sandreas.sandberg@arm.com return isHyp ? vals.armPcElrOffset 25612176Sandreas.sandberg@arm.com : vals.armPcOffset; 25712176Sandreas.sandberg@arm.com } 25812176Sandreas.sandberg@arm.com uint8_t thumbPcOffset(bool isHyp) override { 25912176Sandreas.sandberg@arm.com return isHyp ? vals.thumbPcElrOffset 26012176Sandreas.sandberg@arm.com : vals.thumbPcOffset; 26112176Sandreas.sandberg@arm.com } 26212176Sandreas.sandberg@arm.com uint8_t armPcElrOffset() override { return vals.armPcElrOffset; } 26312176Sandreas.sandberg@arm.com uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; } 26412176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; } 26512176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; } 26612176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; } 26712176Sandreas.sandberg@arm.com uint32_t iss() const override { return issRaw; } 2686019Shines@cs.fsu.edu}; 2696019Shines@cs.fsu.edu 2707400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset> 2717400SAli.Saidi@ARM.com{ 2727400SAli.Saidi@ARM.com public: 27310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 27412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 2757400SAli.Saidi@ARM.com}; 2767189Sgblack@eecs.umich.edu 2777362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 2787189Sgblack@eecs.umich.edu{ 2797189Sgblack@eecs.umich.edu protected: 2807189Sgblack@eecs.umich.edu bool unknown; 2817640Sgblack@eecs.umich.edu bool disabled; 28210037SARM gem5 Developers ExceptionClass overrideEc; 28310205SAli.Saidi@ARM.com const char *mnemonic; 2847189Sgblack@eecs.umich.edu 2857189Sgblack@eecs.umich.edu public: 2867189Sgblack@eecs.umich.edu UndefinedInstruction(ExtMachInst _machInst, 2877189Sgblack@eecs.umich.edu bool _unknown, 2887640Sgblack@eecs.umich.edu const char *_mnemonic = NULL, 2897640Sgblack@eecs.umich.edu bool _disabled = false) : 29010037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst), 29110205SAli.Saidi@ARM.com unknown(_unknown), disabled(_disabled), 29210205SAli.Saidi@ARM.com overrideEc(EC_INVALID), mnemonic(_mnemonic) 29310037SARM gem5 Developers {} 29410205SAli.Saidi@ARM.com UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 29510205SAli.Saidi@ARM.com ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 29610037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 29710205SAli.Saidi@ARM.com unknown(false), disabled(true), overrideEc(_overrideEc), 29810205SAli.Saidi@ARM.com mnemonic(_mnemonic) 2998782Sgblack@eecs.umich.edu {} 3007189Sgblack@eecs.umich.edu 30110417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 30212176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 30312176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 30412176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 30512176Sandreas.sandberg@arm.com uint32_t iss() const override; 3067189Sgblack@eecs.umich.edu}; 3077189Sgblack@eecs.umich.edu 3087362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall> 3097197Sgblack@eecs.umich.edu{ 3107197Sgblack@eecs.umich.edu protected: 31110037SARM gem5 Developers ExceptionClass overrideEc; 3127197Sgblack@eecs.umich.edu public: 31310037SARM gem5 Developers SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 31410037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 31510037SARM gem5 Developers ArmFaultVals<SupervisorCall>(_machInst, _iss), 31610037SARM gem5 Developers overrideEc(_overrideEc) 3178782Sgblack@eecs.umich.edu {} 3187197Sgblack@eecs.umich.edu 31910417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 32012176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 32112176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 32212176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 32312176Sandreas.sandberg@arm.com uint32_t iss() const override; 32410037SARM gem5 Developers}; 32510037SARM gem5 Developers 32610037SARM gem5 Developersclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 32710037SARM gem5 Developers{ 32810037SARM gem5 Developers public: 32910037SARM gem5 Developers SecureMonitorCall(ExtMachInst _machInst) : 33010037SARM gem5 Developers ArmFaultVals<SecureMonitorCall>(_machInst) 33110037SARM gem5 Developers {} 33210037SARM gem5 Developers 33310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 33412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 33512176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 33612176Sandreas.sandberg@arm.com uint32_t iss() const override; 33710037SARM gem5 Developers}; 33810037SARM gem5 Developers 33910037SARM gem5 Developersclass SupervisorTrap : public ArmFaultVals<SupervisorTrap> 34010037SARM gem5 Developers{ 34110037SARM gem5 Developers protected: 34210037SARM gem5 Developers ExtMachInst machInst; 34310037SARM gem5 Developers ExceptionClass overrideEc; 34410037SARM gem5 Developers 34510037SARM gem5 Developers public: 34610037SARM gem5 Developers SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 34710037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 34810037SARM gem5 Developers ArmFaultVals<SupervisorTrap>(_machInst, _iss), 34910037SARM gem5 Developers overrideEc(_overrideEc) 35010037SARM gem5 Developers {} 35110037SARM gem5 Developers 35212509Schuan.zhu@arm.com bool routeToHyp(ThreadContext *tc) const override; 35312509Schuan.zhu@arm.com uint32_t iss() const override; 35412176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 35510037SARM gem5 Developers}; 35610037SARM gem5 Developers 35710037SARM gem5 Developersclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 35810037SARM gem5 Developers{ 35910037SARM gem5 Developers protected: 36010037SARM gem5 Developers ExtMachInst machInst; 36110037SARM gem5 Developers ExceptionClass overrideEc; 36210037SARM gem5 Developers 36310037SARM gem5 Developers public: 36410037SARM gem5 Developers SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 36510037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 36610037SARM gem5 Developers ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 36710037SARM gem5 Developers overrideEc(_overrideEc) 36810037SARM gem5 Developers {} 36910037SARM gem5 Developers 37012176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 37110037SARM gem5 Developers}; 37210037SARM gem5 Developers 37310037SARM gem5 Developersclass HypervisorCall : public ArmFaultVals<HypervisorCall> 37410037SARM gem5 Developers{ 37510037SARM gem5 Developers public: 37610037SARM gem5 Developers HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 37711576SDylan.Johnson@ARM.com 37812176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 37910037SARM gem5 Developers}; 38010037SARM gem5 Developers 38110037SARM gem5 Developersclass HypervisorTrap : public ArmFaultVals<HypervisorTrap> 38210037SARM gem5 Developers{ 38310037SARM gem5 Developers protected: 38410037SARM gem5 Developers ExtMachInst machInst; 38510037SARM gem5 Developers ExceptionClass overrideEc; 38610037SARM gem5 Developers 38710037SARM gem5 Developers public: 38810037SARM gem5 Developers HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 38910037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 39010037SARM gem5 Developers ArmFaultVals<HypervisorTrap>(_machInst, _iss), 39110037SARM gem5 Developers overrideEc(_overrideEc) 39210037SARM gem5 Developers {} 39310037SARM gem5 Developers 39412176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 3957197Sgblack@eecs.umich.edu}; 3967362Sgblack@eecs.umich.edu 3977362Sgblack@eecs.umich.edutemplate <class T> 3987362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T> 3997362Sgblack@eecs.umich.edu{ 4007362Sgblack@eecs.umich.edu protected: 40110037SARM gem5 Developers /** 40210037SARM gem5 Developers * The virtual address the fault occured at. If 2 stages of 40310037SARM gem5 Developers * translation are being used then this is the intermediate 40410037SARM gem5 Developers * physical address that is the starting point for the second 40510037SARM gem5 Developers * stage of translation. 40610037SARM gem5 Developers */ 4077362Sgblack@eecs.umich.edu Addr faultAddr; 40810037SARM gem5 Developers /** 40910037SARM gem5 Developers * Original virtual address. If the fault was generated on the 41010037SARM gem5 Developers * second stage of translation then this variable stores the 41110037SARM gem5 Developers * virtual address used in the original stage 1 translation. 41210037SARM gem5 Developers */ 41310037SARM gem5 Developers Addr OVAddr; 4147362Sgblack@eecs.umich.edu bool write; 41510037SARM gem5 Developers TlbEntry::DomainType domain; 41610037SARM gem5 Developers uint8_t source; 41710037SARM gem5 Developers uint8_t srcEncoded; 41810037SARM gem5 Developers bool stage2; 41910037SARM gem5 Developers bool s1ptw; 42010037SARM gem5 Developers ArmFault::TranMethod tranMethod; 4217362Sgblack@eecs.umich.edu 4227362Sgblack@eecs.umich.edu public: 42310537Sandreas.hansson@arm.com AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, 42410537Sandreas.hansson@arm.com uint8_t _source, bool _stage2, 42510537Sandreas.hansson@arm.com ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 42610537Sandreas.hansson@arm.com faultAddr(_faultAddr), OVAddr(0), write(_write), 42710537Sandreas.hansson@arm.com domain(_domain), source(_source), srcEncoded(0), 42810037SARM gem5 Developers stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 4297362Sgblack@eecs.umich.edu {} 4307362Sgblack@eecs.umich.edu 43110417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 43212176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 43310037SARM gem5 Developers 43412570Sgiacomo.travaglini@arm.com FSR getFsr(ThreadContext *tc) const override; 43512570Sgiacomo.travaglini@arm.com uint8_t getFaultStatusCode(ThreadContext *tc) const; 43612176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 43712176Sandreas.sandberg@arm.com uint32_t iss() const override; 43812176Sandreas.sandberg@arm.com bool isStage2() const override { return stage2; } 43912176Sandreas.sandberg@arm.com void annotate(ArmFault::AnnotationIDs id, uint64_t val) override; 44012570Sgiacomo.travaglini@arm.com void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override; 44110037SARM gem5 Developers bool isMMUFault() const; 4427362Sgblack@eecs.umich.edu}; 4437362Sgblack@eecs.umich.edu 4447362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort> 4457362Sgblack@eecs.umich.edu{ 4467362Sgblack@eecs.umich.edu public: 44710037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_IFSR; 44810037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_IFAR; 44910037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 4507362Sgblack@eecs.umich.edu 45110037SARM gem5 Developers PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 45210037SARM gem5 Developers ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 45310037SARM gem5 Developers AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 45410037SARM gem5 Developers _source, _stage2, _tranMethod) 4557362Sgblack@eecs.umich.edu {} 45610037SARM gem5 Developers 45712176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 45810037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 45912176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 46012176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 4617362Sgblack@eecs.umich.edu}; 4627362Sgblack@eecs.umich.edu 4637362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort> 4647362Sgblack@eecs.umich.edu{ 4657362Sgblack@eecs.umich.edu public: 46610037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 46710037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 46810037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 46910037SARM gem5 Developers bool isv; 47010037SARM gem5 Developers uint8_t sas; 47110037SARM gem5 Developers uint8_t sse; 47210037SARM gem5 Developers uint8_t srt; 4737362Sgblack@eecs.umich.edu 47410037SARM gem5 Developers // AArch64 only 47510037SARM gem5 Developers bool sf; 47610037SARM gem5 Developers bool ar; 47710037SARM gem5 Developers 47810037SARM gem5 Developers DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 47910037SARM gem5 Developers bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 48010037SARM gem5 Developers AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 48110037SARM gem5 Developers _tranMethod), 48210037SARM gem5 Developers isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 4837362Sgblack@eecs.umich.edu {} 48410037SARM gem5 Developers 48512176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 48610037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 48712176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 48812176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 48912176Sandreas.sandberg@arm.com uint32_t iss() const override; 49012176Sandreas.sandberg@arm.com void annotate(AnnotationIDs id, uint64_t val) override; 4917362Sgblack@eecs.umich.edu}; 4927362Sgblack@eecs.umich.edu 49310037SARM gem5 Developersclass VirtualDataAbort : public AbortFault<VirtualDataAbort> 49410037SARM gem5 Developers{ 49510037SARM gem5 Developers public: 49610037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 49710037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 49810037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 49910037SARM gem5 Developers 50010037SARM gem5 Developers VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 50110037SARM gem5 Developers uint8_t _source) : 50210037SARM gem5 Developers AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 50310037SARM gem5 Developers {} 50410037SARM gem5 Developers 50512176Sandreas.sandberg@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 50610037SARM gem5 Developers}; 50710037SARM gem5 Developers 50810037SARM gem5 Developersclass Interrupt : public ArmFaultVals<Interrupt> 50910037SARM gem5 Developers{ 51010037SARM gem5 Developers public: 51112176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 51212176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 51312176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 51410037SARM gem5 Developers}; 51510037SARM gem5 Developers 51610037SARM gem5 Developersclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 51710037SARM gem5 Developers{ 51810037SARM gem5 Developers public: 51910037SARM gem5 Developers VirtualInterrupt(); 52010037SARM gem5 Developers}; 52110037SARM gem5 Developers 52210037SARM gem5 Developersclass FastInterrupt : public ArmFaultVals<FastInterrupt> 52310037SARM gem5 Developers{ 52410037SARM gem5 Developers public: 52512176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 52612176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 52712176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 52812176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext *tc) override; 52910037SARM gem5 Developers}; 53010037SARM gem5 Developers 53110037SARM gem5 Developersclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 53210037SARM gem5 Developers{ 53310037SARM gem5 Developers public: 53410037SARM gem5 Developers VirtualFastInterrupt(); 53510037SARM gem5 Developers}; 53610037SARM gem5 Developers 53710037SARM gem5 Developers/// PC alignment fault (AArch64 only) 53810037SARM gem5 Developersclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 53910037SARM gem5 Developers{ 54010037SARM gem5 Developers protected: 54110037SARM gem5 Developers /// The unaligned value of the PC 54210037SARM gem5 Developers Addr faultPC; 54310037SARM gem5 Developers public: 54410037SARM gem5 Developers PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 54510037SARM gem5 Developers {} 54610417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 54712176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 54812568Sgiacomo.travaglini@arm.com bool routeToHyp(ThreadContext *tc) const override; 54910037SARM gem5 Developers}; 55010037SARM gem5 Developers 55110037SARM gem5 Developers/// Stack pointer alignment fault (AArch64 only) 55210037SARM gem5 Developersclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 55310037SARM gem5 Developers{ 55410037SARM gem5 Developers public: 55510037SARM gem5 Developers SPAlignmentFault(); 55610037SARM gem5 Developers}; 55710037SARM gem5 Developers 55810037SARM gem5 Developers/// System error (AArch64 only) 55910037SARM gem5 Developersclass SystemError : public ArmFaultVals<SystemError> 56010037SARM gem5 Developers{ 56110037SARM gem5 Developers public: 56210037SARM gem5 Developers SystemError(); 56310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 56412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 56512176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 56612176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 56710037SARM gem5 Developers}; 5686019Shines@cs.fsu.edu 56912299Sandreas.sandberg@arm.com/// System error (AArch64 only) 57012299Sandreas.sandberg@arm.comclass SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint> 57112299Sandreas.sandberg@arm.com{ 57212299Sandreas.sandberg@arm.com public: 57312299Sandreas.sandberg@arm.com SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss); 57412299Sandreas.sandberg@arm.com 57512299Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 57612299Sandreas.sandberg@arm.com}; 57712299Sandreas.sandberg@arm.com 5787652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions 5798518Sgeoffrey.blake@arm.comclass ArmSev : public ArmFaultVals<ArmSev> 5808518Sgeoffrey.blake@arm.com{ 5818518Sgeoffrey.blake@arm.com public: 5828518Sgeoffrey.blake@arm.com ArmSev () {} 58310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 58412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 5858518Sgeoffrey.blake@arm.com}; 5868518Sgeoffrey.blake@arm.com 58710037SARM gem5 Developers/// Illegal Instruction Set State fault (AArch64 only) 58810037SARM gem5 Developersclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 58910037SARM gem5 Developers{ 59010037SARM gem5 Developers public: 59110037SARM gem5 Developers IllegalInstSetStateFault(); 59210037SARM gem5 Developers}; 59310037SARM gem5 Developers 59411929SMatteo.Andreozzi@arm.com/* 59512032Sandreas.sandberg@arm.com * Explicitly declare template static member variables to avoid warnings 59612032Sandreas.sandberg@arm.com * in some clang versions 59711929SMatteo.Andreozzi@arm.com */ 59811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals; 59911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals; 60011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals; 60111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals; 60211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals; 60311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals; 60411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals; 60511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals; 60611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals; 60711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals; 60811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals; 60911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals; 61011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals; 61111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals; 61211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals; 61311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals; 61411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals; 61511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals; 61612299Sandreas.sandberg@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals; 61711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals; 61811929SMatteo.Andreozzi@arm.com 61911929SMatteo.Andreozzi@arm.com 6207811Ssteve.reinhardt@amd.com} // namespace ArmISA 6216019Shines@cs.fsu.edu 6226019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__ 623