faults.hh revision 12511
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 37189Sgblack@eecs.umich.edu * All rights reserved 47189Sgblack@eecs.umich.edu * 57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97189Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137189Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 486019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 496019Shines@cs.fsu.edu 507362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5110037SARM gem5 Developers#include "arch/arm/pagetable.hh" 526735Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 5312334Sgabeblack@google.com#include "base/logging.hh" 546019Shines@cs.fsu.edu#include "sim/faults.hh" 558782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 6111294Sandreas.hansson@arm.comtypedef Addr FaultOffset; 626019Shines@cs.fsu.edu 637362Sgblack@eecs.umich.educlass ArmFault : public FaultBase 646019Shines@cs.fsu.edu{ 656019Shines@cs.fsu.edu protected: 6610037SARM gem5 Developers ExtMachInst machInst; 6710037SARM gem5 Developers uint32_t issRaw; 6810037SARM gem5 Developers 6910037SARM gem5 Developers // Helper variables for ARMv8 exception handling 7010037SARM gem5 Developers bool from64; // True if the exception is generated from the AArch64 state 7110037SARM gem5 Developers bool to64; // True if the exception is taken in AArch64 state 7210037SARM gem5 Developers ExceptionLevel fromEL; // Source exception level 7310037SARM gem5 Developers ExceptionLevel toEL; // Target exception level 7410037SARM gem5 Developers OperatingMode fromMode; // Source operating mode 7510037SARM gem5 Developers 7612402Sgiacomo.travaglini@arm.com bool hypRouted; // True if the fault has been routed to Hypervisor 7712402Sgiacomo.travaglini@arm.com 786735Sgblack@eecs.umich.edu Addr getVector(ThreadContext *tc); 7910037SARM gem5 Developers Addr getVector64(ThreadContext *tc); 806735Sgblack@eecs.umich.edu 816019Shines@cs.fsu.edu public: 8210037SARM gem5 Developers /// Generic fault source enums used to index into 8310037SARM gem5 Developers /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 8410037SARM gem5 Developers /// on the current register width state and the translation table format in 8510037SARM gem5 Developers /// use 8610037SARM gem5 Developers enum FaultSource 877362Sgblack@eecs.umich.edu { 8810037SARM gem5 Developers AlignmentFault = 0, 8910037SARM gem5 Developers InstructionCacheMaintenance, // Short-desc. format only 9010037SARM gem5 Developers SynchExtAbtOnTranslTableWalkLL, 9110037SARM gem5 Developers SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 9210037SARM gem5 Developers TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 9310037SARM gem5 Developers AccessFlagLL = TranslationLL + 4, 9410037SARM gem5 Developers DomainLL = AccessFlagLL + 4, 9510037SARM gem5 Developers PermissionLL = DomainLL + 4, 9610037SARM gem5 Developers DebugEvent = PermissionLL + 4, 9710037SARM gem5 Developers SynchronousExternalAbort, 9810037SARM gem5 Developers TLBConflictAbort, // Requires LPAE 9910037SARM gem5 Developers SynchPtyErrOnMemoryAccess, 10010037SARM gem5 Developers AsynchronousExternalAbort, 10110037SARM gem5 Developers AsynchPtyErrOnMemoryAccess, 10210037SARM gem5 Developers AddressSizeLL, // AArch64 only 1037611SGene.Wu@arm.com 10410037SARM gem5 Developers // Not real faults. These are faults to allow the translation function 10510037SARM gem5 Developers // to inform the memory access function not to proceed for a prefetch 10610037SARM gem5 Developers // that misses in the TLB or that targets an uncacheable address 10710037SARM gem5 Developers PrefetchTLBMiss = AddressSizeLL + 4, 10810037SARM gem5 Developers PrefetchUncacheable, 10910037SARM gem5 Developers 11010037SARM gem5 Developers NumFaultSources, 11110037SARM gem5 Developers FaultSourceInvalid = 0xff 11210037SARM gem5 Developers }; 11310037SARM gem5 Developers 11410037SARM gem5 Developers /// Encodings of the fault sources when the short-desc. translation table 11510037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 11610037SARM gem5 Developers static uint8_t shortDescFaultSources[NumFaultSources]; 11710037SARM gem5 Developers /// Encodings of the fault sources when the long-desc. translation table 11810037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 11910037SARM gem5 Developers static uint8_t longDescFaultSources[NumFaultSources]; 12010037SARM gem5 Developers /// Encodings of the fault sources in AArch64 state 12110037SARM gem5 Developers static uint8_t aarch64FaultSources[NumFaultSources]; 12210037SARM gem5 Developers 12310037SARM gem5 Developers enum AnnotationIDs 12410037SARM gem5 Developers { 12510037SARM gem5 Developers S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 12610037SARM gem5 Developers OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 12710037SARM gem5 Developers SAS, // DataAbort: Syndrome Access Size 12810037SARM gem5 Developers SSE, // DataAbort: Syndrome Sign Extend 12910037SARM gem5 Developers SRT, // DataAbort: Syndrome Register Transfer 13010037SARM gem5 Developers 13110037SARM gem5 Developers // AArch64 only 13210037SARM gem5 Developers SF, // DataAbort: width of the accessed register is SixtyFour 13310037SARM gem5 Developers AR // DataAbort: Acquire/Release semantics 13410037SARM gem5 Developers }; 13510037SARM gem5 Developers 13610037SARM gem5 Developers enum TranMethod 13710037SARM gem5 Developers { 13810037SARM gem5 Developers LpaeTran, 13910037SARM gem5 Developers VmsaTran, 14010037SARM gem5 Developers UnknownTran 1417362Sgblack@eecs.umich.edu }; 1427362Sgblack@eecs.umich.edu 1436735Sgblack@eecs.umich.edu struct FaultVals 1446735Sgblack@eecs.umich.edu { 1456735Sgblack@eecs.umich.edu const FaultName name; 14610037SARM gem5 Developers 1476735Sgblack@eecs.umich.edu const FaultOffset offset; 14810037SARM gem5 Developers 14910037SARM gem5 Developers // Offsets used for exceptions taken in AArch64 state 15010037SARM gem5 Developers const uint16_t currELTOffset; 15110037SARM gem5 Developers const uint16_t currELHOffset; 15210037SARM gem5 Developers const uint16_t lowerEL64Offset; 15310037SARM gem5 Developers const uint16_t lowerEL32Offset; 15410037SARM gem5 Developers 1556735Sgblack@eecs.umich.edu const OperatingMode nextMode; 15610037SARM gem5 Developers 1576735Sgblack@eecs.umich.edu const uint8_t armPcOffset; 1586735Sgblack@eecs.umich.edu const uint8_t thumbPcOffset; 15910037SARM gem5 Developers // The following two values are used in place of armPcOffset and 16010037SARM gem5 Developers // thumbPcOffset when the exception return address is saved into ELR 16110037SARM gem5 Developers // registers (exceptions taken in HYP mode or in AArch64 state) 16210037SARM gem5 Developers const uint8_t armPcElrOffset; 16310037SARM gem5 Developers const uint8_t thumbPcElrOffset; 16410037SARM gem5 Developers 16510037SARM gem5 Developers const bool hypTrappable; 1666735Sgblack@eecs.umich.edu const bool abortDisable; 1676735Sgblack@eecs.umich.edu const bool fiqDisable; 16810037SARM gem5 Developers 16910037SARM gem5 Developers // Exception class used to appropriately set the syndrome register 17010037SARM gem5 Developers // (exceptions taken in HYP mode or in AArch64 state) 17110037SARM gem5 Developers const ExceptionClass ec; 17210037SARM gem5 Developers 1736735Sgblack@eecs.umich.edu FaultStat count; 1746735Sgblack@eecs.umich.edu }; 1756735Sgblack@eecs.umich.edu 17610037SARM gem5 Developers ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 17710537Sandreas.hansson@arm.com machInst(_machInst), issRaw(_iss), from64(false), to64(false), 17812402Sgiacomo.travaglini@arm.com fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false) {} 17910037SARM gem5 Developers 18010037SARM gem5 Developers // Returns the actual syndrome register to use based on the target 18110037SARM gem5 Developers // exception level 18210037SARM gem5 Developers MiscRegIndex getSyndromeReg64() const; 18310037SARM gem5 Developers // Returns the actual fault address register to use based on the target 18410037SARM gem5 Developers // exception level 18510037SARM gem5 Developers MiscRegIndex getFaultAddrReg64() const; 18610037SARM gem5 Developers 18710417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 18812176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 18910417Sandreas.hansson@arm.com void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 19010417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 19110037SARM gem5 Developers virtual void annotate(AnnotationIDs id, uint64_t val) {} 1926735Sgblack@eecs.umich.edu virtual FaultStat& countStat() = 0; 19310037SARM gem5 Developers virtual FaultOffset offset(ThreadContext *tc) = 0; 19412511Schuan.zhu@arm.com virtual FaultOffset offset64(ThreadContext *tc) = 0; 1956735Sgblack@eecs.umich.edu virtual OperatingMode nextMode() = 0; 19610037SARM gem5 Developers virtual bool routeToMonitor(ThreadContext *tc) const = 0; 19710037SARM gem5 Developers virtual bool routeToHyp(ThreadContext *tc) const { return false; } 19810037SARM gem5 Developers virtual uint8_t armPcOffset(bool isHyp) = 0; 19910037SARM gem5 Developers virtual uint8_t thumbPcOffset(bool isHyp) = 0; 20010037SARM gem5 Developers virtual uint8_t armPcElrOffset() = 0; 20110037SARM gem5 Developers virtual uint8_t thumbPcElrOffset() = 0; 20210037SARM gem5 Developers virtual bool abortDisable(ThreadContext *tc) = 0; 20310037SARM gem5 Developers virtual bool fiqDisable(ThreadContext *tc) = 0; 20410037SARM gem5 Developers virtual ExceptionClass ec(ThreadContext *tc) const = 0; 20510037SARM gem5 Developers virtual uint32_t iss() const = 0; 20610037SARM gem5 Developers virtual bool isStage2() const { return false; } 20710037SARM gem5 Developers virtual FSR getFsr(ThreadContext *tc) { return 0; } 20810037SARM gem5 Developers virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 2096019Shines@cs.fsu.edu}; 2106019Shines@cs.fsu.edu 2116735Sgblack@eecs.umich.edutemplate<typename T> 2127362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault 2136019Shines@cs.fsu.edu{ 2146735Sgblack@eecs.umich.edu protected: 2156735Sgblack@eecs.umich.edu static FaultVals vals; 2166735Sgblack@eecs.umich.edu 2176019Shines@cs.fsu.edu public: 21810037SARM gem5 Developers ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 21910037SARM gem5 Developers ArmFault(_machInst, _iss) {} 22012176Sandreas.sandberg@arm.com FaultName name() const override { return vals.name; } 22112176Sandreas.sandberg@arm.com FaultStat & countStat() override { return vals.count; } 22212176Sandreas.sandberg@arm.com FaultOffset offset(ThreadContext *tc) override; 22310037SARM gem5 Developers 22412511Schuan.zhu@arm.com FaultOffset offset64(ThreadContext *tc) override; 22510037SARM gem5 Developers 22612176Sandreas.sandberg@arm.com OperatingMode nextMode() override { return vals.nextMode; } 22712176Sandreas.sandberg@arm.com virtual bool routeToMonitor(ThreadContext *tc) const override { 22812176Sandreas.sandberg@arm.com return false; 22912176Sandreas.sandberg@arm.com } 23012176Sandreas.sandberg@arm.com uint8_t armPcOffset(bool isHyp) override { 23112176Sandreas.sandberg@arm.com return isHyp ? vals.armPcElrOffset 23212176Sandreas.sandberg@arm.com : vals.armPcOffset; 23312176Sandreas.sandberg@arm.com } 23412176Sandreas.sandberg@arm.com uint8_t thumbPcOffset(bool isHyp) override { 23512176Sandreas.sandberg@arm.com return isHyp ? vals.thumbPcElrOffset 23612176Sandreas.sandberg@arm.com : vals.thumbPcOffset; 23712176Sandreas.sandberg@arm.com } 23812176Sandreas.sandberg@arm.com uint8_t armPcElrOffset() override { return vals.armPcElrOffset; } 23912176Sandreas.sandberg@arm.com uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; } 24012176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; } 24112176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; } 24212176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; } 24312176Sandreas.sandberg@arm.com uint32_t iss() const override { return issRaw; } 2446019Shines@cs.fsu.edu}; 2456019Shines@cs.fsu.edu 2467400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset> 2477400SAli.Saidi@ARM.com{ 2487400SAli.Saidi@ARM.com public: 24910417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 25012176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 2517400SAli.Saidi@ARM.com}; 2527189Sgblack@eecs.umich.edu 2537362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 2547189Sgblack@eecs.umich.edu{ 2557189Sgblack@eecs.umich.edu protected: 2567189Sgblack@eecs.umich.edu bool unknown; 2577640Sgblack@eecs.umich.edu bool disabled; 25810037SARM gem5 Developers ExceptionClass overrideEc; 25910205SAli.Saidi@ARM.com const char *mnemonic; 2607189Sgblack@eecs.umich.edu 2617189Sgblack@eecs.umich.edu public: 2627189Sgblack@eecs.umich.edu UndefinedInstruction(ExtMachInst _machInst, 2637189Sgblack@eecs.umich.edu bool _unknown, 2647640Sgblack@eecs.umich.edu const char *_mnemonic = NULL, 2657640Sgblack@eecs.umich.edu bool _disabled = false) : 26610037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst), 26710205SAli.Saidi@ARM.com unknown(_unknown), disabled(_disabled), 26810205SAli.Saidi@ARM.com overrideEc(EC_INVALID), mnemonic(_mnemonic) 26910037SARM gem5 Developers {} 27010205SAli.Saidi@ARM.com UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 27110205SAli.Saidi@ARM.com ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 27210037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 27310205SAli.Saidi@ARM.com unknown(false), disabled(true), overrideEc(_overrideEc), 27410205SAli.Saidi@ARM.com mnemonic(_mnemonic) 2758782Sgblack@eecs.umich.edu {} 2767189Sgblack@eecs.umich.edu 27710417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 27812176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 27912176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 28012176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 28112176Sandreas.sandberg@arm.com uint32_t iss() const override; 2827189Sgblack@eecs.umich.edu}; 2837189Sgblack@eecs.umich.edu 2847362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall> 2857197Sgblack@eecs.umich.edu{ 2867197Sgblack@eecs.umich.edu protected: 28710037SARM gem5 Developers ExceptionClass overrideEc; 2887197Sgblack@eecs.umich.edu public: 28910037SARM gem5 Developers SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 29010037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 29110037SARM gem5 Developers ArmFaultVals<SupervisorCall>(_machInst, _iss), 29210037SARM gem5 Developers overrideEc(_overrideEc) 2938782Sgblack@eecs.umich.edu {} 2947197Sgblack@eecs.umich.edu 29510417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 29612176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 29712176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 29812176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 29912176Sandreas.sandberg@arm.com uint32_t iss() const override; 30010037SARM gem5 Developers}; 30110037SARM gem5 Developers 30210037SARM gem5 Developersclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 30310037SARM gem5 Developers{ 30410037SARM gem5 Developers public: 30510037SARM gem5 Developers SecureMonitorCall(ExtMachInst _machInst) : 30610037SARM gem5 Developers ArmFaultVals<SecureMonitorCall>(_machInst) 30710037SARM gem5 Developers {} 30810037SARM gem5 Developers 30910417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 31012176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 31112176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 31212176Sandreas.sandberg@arm.com uint32_t iss() const override; 31310037SARM gem5 Developers}; 31410037SARM gem5 Developers 31510037SARM gem5 Developersclass SupervisorTrap : public ArmFaultVals<SupervisorTrap> 31610037SARM gem5 Developers{ 31710037SARM gem5 Developers protected: 31810037SARM gem5 Developers ExtMachInst machInst; 31910037SARM gem5 Developers ExceptionClass overrideEc; 32010037SARM gem5 Developers 32110037SARM gem5 Developers public: 32210037SARM gem5 Developers SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 32310037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 32410037SARM gem5 Developers ArmFaultVals<SupervisorTrap>(_machInst, _iss), 32510037SARM gem5 Developers overrideEc(_overrideEc) 32610037SARM gem5 Developers {} 32710037SARM gem5 Developers 32812509Schuan.zhu@arm.com bool routeToHyp(ThreadContext *tc) const override; 32912509Schuan.zhu@arm.com uint32_t iss() const override; 33012176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 33110037SARM gem5 Developers}; 33210037SARM gem5 Developers 33310037SARM gem5 Developersclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 33410037SARM gem5 Developers{ 33510037SARM gem5 Developers protected: 33610037SARM gem5 Developers ExtMachInst machInst; 33710037SARM gem5 Developers ExceptionClass overrideEc; 33810037SARM gem5 Developers 33910037SARM gem5 Developers public: 34010037SARM gem5 Developers SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 34110037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 34210037SARM gem5 Developers ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 34310037SARM gem5 Developers overrideEc(_overrideEc) 34410037SARM gem5 Developers {} 34510037SARM gem5 Developers 34612176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 34710037SARM gem5 Developers}; 34810037SARM gem5 Developers 34910037SARM gem5 Developersclass HypervisorCall : public ArmFaultVals<HypervisorCall> 35010037SARM gem5 Developers{ 35110037SARM gem5 Developers public: 35210037SARM gem5 Developers HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 35311576SDylan.Johnson@ARM.com 35412176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 35510037SARM gem5 Developers}; 35610037SARM gem5 Developers 35710037SARM gem5 Developersclass HypervisorTrap : public ArmFaultVals<HypervisorTrap> 35810037SARM gem5 Developers{ 35910037SARM gem5 Developers protected: 36010037SARM gem5 Developers ExtMachInst machInst; 36110037SARM gem5 Developers ExceptionClass overrideEc; 36210037SARM gem5 Developers 36310037SARM gem5 Developers public: 36410037SARM gem5 Developers HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 36510037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 36610037SARM gem5 Developers ArmFaultVals<HypervisorTrap>(_machInst, _iss), 36710037SARM gem5 Developers overrideEc(_overrideEc) 36810037SARM gem5 Developers {} 36910037SARM gem5 Developers 37012176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 3717197Sgblack@eecs.umich.edu}; 3727362Sgblack@eecs.umich.edu 3737362Sgblack@eecs.umich.edutemplate <class T> 3747362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T> 3757362Sgblack@eecs.umich.edu{ 3767362Sgblack@eecs.umich.edu protected: 37710037SARM gem5 Developers /** 37810037SARM gem5 Developers * The virtual address the fault occured at. If 2 stages of 37910037SARM gem5 Developers * translation are being used then this is the intermediate 38010037SARM gem5 Developers * physical address that is the starting point for the second 38110037SARM gem5 Developers * stage of translation. 38210037SARM gem5 Developers */ 3837362Sgblack@eecs.umich.edu Addr faultAddr; 38410037SARM gem5 Developers /** 38510037SARM gem5 Developers * Original virtual address. If the fault was generated on the 38610037SARM gem5 Developers * second stage of translation then this variable stores the 38710037SARM gem5 Developers * virtual address used in the original stage 1 translation. 38810037SARM gem5 Developers */ 38910037SARM gem5 Developers Addr OVAddr; 3907362Sgblack@eecs.umich.edu bool write; 39110037SARM gem5 Developers TlbEntry::DomainType domain; 39210037SARM gem5 Developers uint8_t source; 39310037SARM gem5 Developers uint8_t srcEncoded; 39410037SARM gem5 Developers bool stage2; 39510037SARM gem5 Developers bool s1ptw; 39610037SARM gem5 Developers ArmFault::TranMethod tranMethod; 3977362Sgblack@eecs.umich.edu 3987362Sgblack@eecs.umich.edu public: 39910537Sandreas.hansson@arm.com AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, 40010537Sandreas.hansson@arm.com uint8_t _source, bool _stage2, 40110537Sandreas.hansson@arm.com ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 40210537Sandreas.hansson@arm.com faultAddr(_faultAddr), OVAddr(0), write(_write), 40310537Sandreas.hansson@arm.com domain(_domain), source(_source), srcEncoded(0), 40410037SARM gem5 Developers stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 4057362Sgblack@eecs.umich.edu {} 4067362Sgblack@eecs.umich.edu 40710417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 40812176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 40910037SARM gem5 Developers 41012176Sandreas.sandberg@arm.com FSR getFsr(ThreadContext *tc) override; 41112176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 41212176Sandreas.sandberg@arm.com uint32_t iss() const override; 41312176Sandreas.sandberg@arm.com bool isStage2() const override { return stage2; } 41412176Sandreas.sandberg@arm.com void annotate(ArmFault::AnnotationIDs id, uint64_t val) override; 41510037SARM gem5 Developers bool isMMUFault() const; 4167362Sgblack@eecs.umich.edu}; 4177362Sgblack@eecs.umich.edu 4187362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort> 4197362Sgblack@eecs.umich.edu{ 4207362Sgblack@eecs.umich.edu public: 42110037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_IFSR; 42210037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_IFAR; 42310037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 4247362Sgblack@eecs.umich.edu 42510037SARM gem5 Developers PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 42610037SARM gem5 Developers ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 42710037SARM gem5 Developers AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 42810037SARM gem5 Developers _source, _stage2, _tranMethod) 4297362Sgblack@eecs.umich.edu {} 43010037SARM gem5 Developers 43112176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 43210037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 43312176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 43412176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 4357362Sgblack@eecs.umich.edu}; 4367362Sgblack@eecs.umich.edu 4377362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort> 4387362Sgblack@eecs.umich.edu{ 4397362Sgblack@eecs.umich.edu public: 44010037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 44110037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 44210037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 44310037SARM gem5 Developers bool isv; 44410037SARM gem5 Developers uint8_t sas; 44510037SARM gem5 Developers uint8_t sse; 44610037SARM gem5 Developers uint8_t srt; 4477362Sgblack@eecs.umich.edu 44810037SARM gem5 Developers // AArch64 only 44910037SARM gem5 Developers bool sf; 45010037SARM gem5 Developers bool ar; 45110037SARM gem5 Developers 45210037SARM gem5 Developers DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 45310037SARM gem5 Developers bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 45410037SARM gem5 Developers AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 45510037SARM gem5 Developers _tranMethod), 45610037SARM gem5 Developers isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 4577362Sgblack@eecs.umich.edu {} 45810037SARM gem5 Developers 45912176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 46010037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 46112176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 46212176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 46312176Sandreas.sandberg@arm.com uint32_t iss() const override; 46412176Sandreas.sandberg@arm.com void annotate(AnnotationIDs id, uint64_t val) override; 4657362Sgblack@eecs.umich.edu}; 4667362Sgblack@eecs.umich.edu 46710037SARM gem5 Developersclass VirtualDataAbort : public AbortFault<VirtualDataAbort> 46810037SARM gem5 Developers{ 46910037SARM gem5 Developers public: 47010037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 47110037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 47210037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 47310037SARM gem5 Developers 47410037SARM gem5 Developers VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 47510037SARM gem5 Developers uint8_t _source) : 47610037SARM gem5 Developers AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 47710037SARM gem5 Developers {} 47810037SARM gem5 Developers 47912176Sandreas.sandberg@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 48010037SARM gem5 Developers}; 48110037SARM gem5 Developers 48210037SARM gem5 Developersclass Interrupt : public ArmFaultVals<Interrupt> 48310037SARM gem5 Developers{ 48410037SARM gem5 Developers public: 48512176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 48612176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 48712176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 48810037SARM gem5 Developers}; 48910037SARM gem5 Developers 49010037SARM gem5 Developersclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 49110037SARM gem5 Developers{ 49210037SARM gem5 Developers public: 49310037SARM gem5 Developers VirtualInterrupt(); 49410037SARM gem5 Developers}; 49510037SARM gem5 Developers 49610037SARM gem5 Developersclass FastInterrupt : public ArmFaultVals<FastInterrupt> 49710037SARM gem5 Developers{ 49810037SARM gem5 Developers public: 49912176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 50012176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 50112176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 50212176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext *tc) override; 50310037SARM gem5 Developers}; 50410037SARM gem5 Developers 50510037SARM gem5 Developersclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 50610037SARM gem5 Developers{ 50710037SARM gem5 Developers public: 50810037SARM gem5 Developers VirtualFastInterrupt(); 50910037SARM gem5 Developers}; 51010037SARM gem5 Developers 51110037SARM gem5 Developers/// PC alignment fault (AArch64 only) 51210037SARM gem5 Developersclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 51310037SARM gem5 Developers{ 51410037SARM gem5 Developers protected: 51510037SARM gem5 Developers /// The unaligned value of the PC 51610037SARM gem5 Developers Addr faultPC; 51710037SARM gem5 Developers public: 51810037SARM gem5 Developers PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 51910037SARM gem5 Developers {} 52010417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 52112176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 52210037SARM gem5 Developers}; 52310037SARM gem5 Developers 52410037SARM gem5 Developers/// Stack pointer alignment fault (AArch64 only) 52510037SARM gem5 Developersclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 52610037SARM gem5 Developers{ 52710037SARM gem5 Developers public: 52810037SARM gem5 Developers SPAlignmentFault(); 52910037SARM gem5 Developers}; 53010037SARM gem5 Developers 53110037SARM gem5 Developers/// System error (AArch64 only) 53210037SARM gem5 Developersclass SystemError : public ArmFaultVals<SystemError> 53310037SARM gem5 Developers{ 53410037SARM gem5 Developers public: 53510037SARM gem5 Developers SystemError(); 53610417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 53712176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 53812176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 53912176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 54010037SARM gem5 Developers}; 5416019Shines@cs.fsu.edu 54212299Sandreas.sandberg@arm.com/// System error (AArch64 only) 54312299Sandreas.sandberg@arm.comclass SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint> 54412299Sandreas.sandberg@arm.com{ 54512299Sandreas.sandberg@arm.com public: 54612299Sandreas.sandberg@arm.com SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss); 54712299Sandreas.sandberg@arm.com 54812299Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 54912299Sandreas.sandberg@arm.com}; 55012299Sandreas.sandberg@arm.com 5517652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions 5528518Sgeoffrey.blake@arm.comclass ArmSev : public ArmFaultVals<ArmSev> 5538518Sgeoffrey.blake@arm.com{ 5548518Sgeoffrey.blake@arm.com public: 5558518Sgeoffrey.blake@arm.com ArmSev () {} 55610417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 55712176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 5588518Sgeoffrey.blake@arm.com}; 5598518Sgeoffrey.blake@arm.com 56010037SARM gem5 Developers/// Illegal Instruction Set State fault (AArch64 only) 56110037SARM gem5 Developersclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 56210037SARM gem5 Developers{ 56310037SARM gem5 Developers public: 56410037SARM gem5 Developers IllegalInstSetStateFault(); 56510037SARM gem5 Developers}; 56610037SARM gem5 Developers 56711929SMatteo.Andreozzi@arm.com/* 56812032Sandreas.sandberg@arm.com * Explicitly declare template static member variables to avoid warnings 56912032Sandreas.sandberg@arm.com * in some clang versions 57011929SMatteo.Andreozzi@arm.com */ 57111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals; 57211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals; 57311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals; 57411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals; 57511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals; 57611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals; 57711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals; 57811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals; 57911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals; 58011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals; 58111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals; 58211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals; 58311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals; 58411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals; 58511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals; 58611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals; 58711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals; 58811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals; 58912299Sandreas.sandberg@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals; 59011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals; 59111929SMatteo.Andreozzi@arm.com 59211929SMatteo.Andreozzi@arm.com 5937811Ssteve.reinhardt@amd.com} // namespace ArmISA 5946019Shines@cs.fsu.edu 5956019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__ 596