SConscript revision 13168:4965381c122d
16928SN/A# -*- mode:python -*- 26928SN/A 311680SN/A# Copyright (c) 2009, 2012-2013, 2018 ARM Limited 411680SN/A# All rights reserved. 511680SN/A# 66928SN/A# The license below extends only to copyright in the software and shall 711860Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 811860Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 911860Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 1010036SN/A# licensed hereunder. You may use the software subject to the license 1110036SN/A# terms below provided that you ensure that this notice is replicated 1211680SN/A# unmodified and in its entirety in all distributions of the software, 1311680SN/A# modified or unmodified, in source code or in binary form. 1411680SN/A# 1511680SN/A# Copyright (c) 2007-2008 The Florida State University 1611680SN/A# All rights reserved. 1711680SN/A# 1811680SN/A# Redistribution and use in source and binary forms, with or without 1911680SN/A# modification, are permitted provided that the following conditions are 2011680SN/A# met: redistributions of source code must retain the above copyright 2111680SN/A# notice, this list of conditions and the following disclaimer; 2211680SN/A# redistributions in binary form must reproduce the above copyright 2311680SN/A# notice, this list of conditions and the following disclaimer in the 2411680SN/A# documentation and/or other materials provided with the distribution; 2511680SN/A# neither the name of the copyright holders nor the names of its 2611680SN/A# contributors may be used to endorse or promote products derived from 2711680SN/A# this software without specific prior written permission. 2811680SN/A# 2911680SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011680SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111680SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211680SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311680SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411680SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511680SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611680SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711680SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810526SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911680SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011268SN/A# 4111680SN/A# Authors: Stephen Hines 4211680SN/A# Ali Saidi 4310526SN/A 4410526SN/AImport('*') 4510526SN/A 4610526SN/Aif env['TARGET_ISA'] == 'arm': 4710526SN/A# Workaround for bug in SCons version > 0.97d20071212 4810526SN/A# Scons bug id: 2006 M5 Bug id: 308 4910526SN/A Dir('isa/formats') 5010526SN/A Source('decoder.cc') 5110526SN/A Source('faults.cc') 5210526SN/A Source('insts/branch.cc') 5310526SN/A Source('insts/branch64.cc') 5410526SN/A Source('insts/data64.cc') 5511680SN/A Source('insts/macromem.cc') 5611680SN/A Source('insts/mem.cc') 5711680SN/A Source('insts/mem64.cc') 5811680SN/A Source('insts/misc.cc') 5910526SN/A Source('insts/misc64.cc') 6010526SN/A Source('insts/pred_inst.cc') 6110526SN/A Source('insts/pseudo.cc') 6210526SN/A Source('insts/static_inst.cc') 6310526SN/A Source('insts/vfp.cc') 6410526SN/A Source('insts/fplib.cc') 6510526SN/A Source('insts/crypto.cc') 6610526SN/A Source('interrupts.cc') 6710526SN/A Source('isa.cc') 6810526SN/A Source('isa_device.cc') 6910526SN/A Source('linux/linux.cc') 7010526SN/A Source('linux/process.cc') 7110526SN/A Source('linux/system.cc') 7210526SN/A Source('freebsd/freebsd.cc') 7311680SN/A Source('freebsd/process.cc') 7410526SN/A Source('freebsd/system.cc') 7510526SN/A Source('miscregs.cc') 7610526SN/A Source('nativetrace.cc') 7710526SN/A Source('pmu.cc') 7810526SN/A Source('process.cc') 7910526SN/A Source('remote_gdb.cc') 8011680SN/A Source('semihosting.cc') 8110526SN/A Source('stacktrace.cc') 8210526SN/A Source('system.cc') 8310526SN/A Source('table_walker.cc') 8410526SN/A Source('stage2_mmu.cc') 8510526SN/A Source('stage2_lookup.cc') 8610526SN/A Source('tlb.cc') 8711680SN/A Source('tlbi_op.cc') 8811680SN/A Source('utility.cc') 8911680SN/A Source('vtophys.cc') 9011680SN/A 9111680SN/A SimObject('ArmInterrupts.py') 9210526SN/A SimObject('ArmISA.py') 9310526SN/A SimObject('ArmNativeTrace.py') 9410526SN/A SimObject('ArmSemihosting.py') 9510526SN/A SimObject('ArmSystem.py') 9610526SN/A SimObject('ArmTLB.py') 9710526SN/A SimObject('ArmPMU.py') 9810526SN/A 9910526SN/A DebugFlag('Arm') 10010526SN/A DebugFlag('Semihosting') 10110526SN/A DebugFlag('Decoder', "Instructions returned by the predecoder") 10210526SN/A DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") 10310526SN/A DebugFlag('PMUVerbose', "Performance Monitor") 10410526SN/A DebugFlag('TLBVerbose') 10510526SN/A 10610526SN/A # Add files generated by the ISA description. 10710526SN/A ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6) 10810526SN/A