SConscript revision 10461:afeb5cdb3907
113023Sgiacomo.travaglini@arm.com# -*- mode:python -*- 213023Sgiacomo.travaglini@arm.com 313023Sgiacomo.travaglini@arm.com# Copyright (c) 2009, 2012-2013 ARM Limited 413023Sgiacomo.travaglini@arm.com# All rights reserved. 513023Sgiacomo.travaglini@arm.com# 613023Sgiacomo.travaglini@arm.com# The license below extends only to copyright in the software and shall 713023Sgiacomo.travaglini@arm.com# not be construed as granting a license to any other intellectual 813023Sgiacomo.travaglini@arm.com# property including but not limited to intellectual property relating 913023Sgiacomo.travaglini@arm.com# to a hardware implementation of the functionality of the software 1013023Sgiacomo.travaglini@arm.com# licensed hereunder. You may use the software subject to the license 1113023Sgiacomo.travaglini@arm.com# terms below provided that you ensure that this notice is replicated 1213023Sgiacomo.travaglini@arm.com# unmodified and in its entirety in all distributions of the software, 1313023Sgiacomo.travaglini@arm.com# modified or unmodified, in source code or in binary form. 1413023Sgiacomo.travaglini@arm.com# 1513023Sgiacomo.travaglini@arm.com# Copyright (c) 2007-2008 The Florida State University 1613023Sgiacomo.travaglini@arm.com# All rights reserved. 1713023Sgiacomo.travaglini@arm.com# 1813023Sgiacomo.travaglini@arm.com# Redistribution and use in source and binary forms, with or without 1913023Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are 2013023Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright 2113023Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer; 2213023Sgiacomo.travaglini@arm.com# redistributions in binary form must reproduce the above copyright 2313023Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer in the 2413023Sgiacomo.travaglini@arm.com# documentation and/or other materials provided with the distribution; 2513023Sgiacomo.travaglini@arm.com# neither the name of the copyright holders nor the names of its 2613023Sgiacomo.travaglini@arm.com# contributors may be used to endorse or promote products derived from 2713023Sgiacomo.travaglini@arm.com# this software without specific prior written permission. 2813023Sgiacomo.travaglini@arm.com# 2913023Sgiacomo.travaglini@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3013023Sgiacomo.travaglini@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3113023Sgiacomo.travaglini@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3213023Sgiacomo.travaglini@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3313023Sgiacomo.travaglini@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3413023Sgiacomo.travaglini@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3513023Sgiacomo.travaglini@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3613023Sgiacomo.travaglini@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3713023Sgiacomo.travaglini@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3813023Sgiacomo.travaglini@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3913023Sgiacomo.travaglini@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4013023Sgiacomo.travaglini@arm.com# 4113023Sgiacomo.travaglini@arm.com# Authors: Stephen Hines 4213023Sgiacomo.travaglini@arm.com# Ali Saidi 4313023Sgiacomo.travaglini@arm.com 4413023Sgiacomo.travaglini@arm.comImport('*') 4513023Sgiacomo.travaglini@arm.com 4613023Sgiacomo.travaglini@arm.comif env['TARGET_ISA'] == 'arm': 4713023Sgiacomo.travaglini@arm.com# Workaround for bug in SCons version > 0.97d20071212 4813023Sgiacomo.travaglini@arm.com# Scons bug id: 2006 M5 Bug id: 308 4913023Sgiacomo.travaglini@arm.com Dir('isa/formats') 5013023Sgiacomo.travaglini@arm.com Source('decoder.cc') 5113023Sgiacomo.travaglini@arm.com Source('faults.cc') 5213023Sgiacomo.travaglini@arm.com Source('insts/branch64.cc') 5313023Sgiacomo.travaglini@arm.com Source('insts/data64.cc') 5413023Sgiacomo.travaglini@arm.com Source('insts/macromem.cc') 5513023Sgiacomo.travaglini@arm.com Source('insts/mem.cc') 5613023Sgiacomo.travaglini@arm.com Source('insts/mem64.cc') 5713023Sgiacomo.travaglini@arm.com Source('insts/misc.cc') 5813023Sgiacomo.travaglini@arm.com Source('insts/misc64.cc') 5913023Sgiacomo.travaglini@arm.com Source('insts/pred_inst.cc') 6013023Sgiacomo.travaglini@arm.com Source('insts/static_inst.cc') 6113023Sgiacomo.travaglini@arm.com Source('insts/vfp.cc') 6213023Sgiacomo.travaglini@arm.com Source('insts/fplib.cc') 6313023Sgiacomo.travaglini@arm.com Source('interrupts.cc') 6413023Sgiacomo.travaglini@arm.com Source('isa.cc') 6513023Sgiacomo.travaglini@arm.com Source('isa_device.cc') 6613023Sgiacomo.travaglini@arm.com Source('linux/linux.cc') 6713023Sgiacomo.travaglini@arm.com Source('linux/process.cc') 6813023Sgiacomo.travaglini@arm.com Source('linux/system.cc') 6913023Sgiacomo.travaglini@arm.com Source('miscregs.cc') 7013023Sgiacomo.travaglini@arm.com Source('nativetrace.cc') 7113023Sgiacomo.travaglini@arm.com Source('pmu.cc') 7213023Sgiacomo.travaglini@arm.com Source('process.cc') 7313023Sgiacomo.travaglini@arm.com Source('remote_gdb.cc') 7413023Sgiacomo.travaglini@arm.com Source('stacktrace.cc') 7513023Sgiacomo.travaglini@arm.com Source('system.cc') 7613023Sgiacomo.travaglini@arm.com Source('table_walker.cc') 7713023Sgiacomo.travaglini@arm.com Source('stage2_mmu.cc') 7813023Sgiacomo.travaglini@arm.com Source('stage2_lookup.cc') 7913023Sgiacomo.travaglini@arm.com Source('tlb.cc') 8013023Sgiacomo.travaglini@arm.com Source('utility.cc') 8113023Sgiacomo.travaglini@arm.com Source('vtophys.cc') 8213023Sgiacomo.travaglini@arm.com 8313023Sgiacomo.travaglini@arm.com SimObject('ArmInterrupts.py') 8413023Sgiacomo.travaglini@arm.com SimObject('ArmISA.py') 8513023Sgiacomo.travaglini@arm.com SimObject('ArmNativeTrace.py') 8613023Sgiacomo.travaglini@arm.com SimObject('ArmSystem.py') 8713023Sgiacomo.travaglini@arm.com SimObject('ArmTLB.py') 8813023Sgiacomo.travaglini@arm.com SimObject('ArmPMU.py') 8913023Sgiacomo.travaglini@arm.com 9013023Sgiacomo.travaglini@arm.com DebugFlag('Arm') 9113023Sgiacomo.travaglini@arm.com DebugFlag('Decoder', "Instructions returned by the predecoder") 9213023Sgiacomo.travaglini@arm.com DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") 9313023Sgiacomo.travaglini@arm.com DebugFlag('PMUVerbose', "Performance Monitor") 9413023Sgiacomo.travaglini@arm.com DebugFlag('TLBVerbose') 9513023Sgiacomo.travaglini@arm.com 9613023Sgiacomo.travaglini@arm.com # Add files generated by the ISA description. 9713023Sgiacomo.travaglini@arm.com env.ISADesc('isa/main.isa') 9813023Sgiacomo.travaglini@arm.com