xref: /gem5/src/arch/arm/SConscript

# -*- mode:python -*-

# Copyright (c) 2009, 2012-2013 ARM Limited
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# The license below extends only to copyright in the software and shall
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# property including but not limited to intellectual property relating
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# licensed hereunder.  You may use the software subject to the license
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# modified or unmodified, in source code or in binary form.
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# Copyright (c) 2007-2008 The Florida State University
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# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
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# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# Authors: Stephen Hines
#          Ali Saidi

Import('*')

if env['TARGET_ISA'] == 'arm':
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308 
    Dir('isa/formats')
    Source('decoder.cc')
    Source('faults.cc')
    Source('insts/branch64.cc')
    Source('insts/data64.cc')
    Source('insts/macromem.cc')
    Source('insts/mem.cc')
    Source('insts/mem64.cc')
    Source('insts/misc.cc')
    Source('insts/misc64.cc')
    Source('insts/pred_inst.cc')
    Source('insts/static_inst.cc')
    Source('insts/vfp.cc')
    Source('insts/fplib.cc')
    Source('interrupts.cc')
    Source('isa.cc')
    Source('linux/linux.cc')
    Source('linux/process.cc')
    Source('linux/system.cc')
    Source('miscregs.cc')
    Source('nativetrace.cc')
    Source('process.cc')
    Source('remote_gdb.cc')
    Source('stacktrace.cc')
    Source('system.cc')
    Source('table_walker.cc')
    Source('stage2_mmu.cc')
    Source('stage2_lookup.cc')
    Source('tlb.cc')
    Source('utility.cc')
    Source('vtophys.cc')

    SimObject('ArmInterrupts.py')
    SimObject('ArmISA.py')
    SimObject('ArmNativeTrace.py')
    SimObject('ArmSystem.py')
    SimObject('ArmTLB.py')

    DebugFlag('Arm')
    DebugFlag('Decoder', "Instructions returned by the predecoder")
    DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
    DebugFlag('TLBVerbose')

    # Add files generated by the ISA description.
    env.ISADesc('isa/main.isa')