ArmTLB.py revision 13665
16019Shines@cs.fsu.edu# -*- mode:python -*- 26019Shines@cs.fsu.edu 310717Sandreas.hansson@arm.com# Copyright (c) 2009, 2013, 2015 ARM Limited 46019Shines@cs.fsu.edu# All rights reserved. 56019Shines@cs.fsu.edu# 67404SAli.Saidi@ARM.com# The license below extends only to copyright in the software and shall 77404SAli.Saidi@ARM.com# not be construed as granting a license to any other intellectual 87404SAli.Saidi@ARM.com# property including but not limited to intellectual property relating 97404SAli.Saidi@ARM.com# to a hardware implementation of the functionality of the software 107404SAli.Saidi@ARM.com# licensed hereunder. You may use the software subject to the license 117404SAli.Saidi@ARM.com# terms below provided that you ensure that this notice is replicated 127404SAli.Saidi@ARM.com# unmodified and in its entirety in all distributions of the software, 137404SAli.Saidi@ARM.com# modified or unmodified, in source code or in binary form. 147404SAli.Saidi@ARM.com# 156019Shines@cs.fsu.edu# Redistribution and use in source and binary forms, with or without 166019Shines@cs.fsu.edu# modification, are permitted provided that the following conditions are 176019Shines@cs.fsu.edu# met: redistributions of source code must retain the above copyright 186019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer; 196019Shines@cs.fsu.edu# redistributions in binary form must reproduce the above copyright 206019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer in the 216019Shines@cs.fsu.edu# documentation and/or other materials provided with the distribution; 226019Shines@cs.fsu.edu# neither the name of the copyright holders nor the names of its 236019Shines@cs.fsu.edu# contributors may be used to endorse or promote products derived from 246019Shines@cs.fsu.edu# this software without specific prior written permission. 256019Shines@cs.fsu.edu# 266019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 276019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 286019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 296019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 306019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 316019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 326019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 336019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 346019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 356019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 366019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376019Shines@cs.fsu.edu# 387404SAli.Saidi@ARM.com# Authors: Ali Saidi 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.edufrom m5.SimObject import SimObject 416019Shines@cs.fsu.edufrom m5.params import * 427404SAli.Saidi@ARM.comfrom m5.proxy import * 4313665Sandreas.sandberg@arm.comfrom m5.objects.MemObject import MemObject 4413665Sandreas.sandberg@arm.comfrom m5.objects.BaseTLB import BaseTLB 457404SAli.Saidi@ARM.com 4610037SARM gem5 Developers# Basic stage 1 translation objects 478756Sgblack@eecs.umich.educlass ArmTableWalker(MemObject): 488756Sgblack@eecs.umich.edu type = 'ArmTableWalker' 498756Sgblack@eecs.umich.edu cxx_class = 'ArmISA::TableWalker' 509338SAndreas.Sandberg@arm.com cxx_header = "arch/arm/table_walker.hh" 5110037SARM gem5 Developers is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?") 529258SAli.Saidi@ARM.com num_squash_per_cycle = Param.Unsigned(2, 539258SAli.Saidi@ARM.com "Number of outstanding walks that can be squashed per cycle") 546019Shines@cs.fsu.edu 5510717Sandreas.hansson@arm.com # The port to the memory system. This port is ultimately belonging 5610717Sandreas.hansson@arm.com # to the Stage2MMU, and shared by the two table walkers, but we 5710717Sandreas.hansson@arm.com # access it through the ITB and DTB walked objects in the CPU for 5810717Sandreas.hansson@arm.com # symmetry with the other ISAs. 5910717Sandreas.hansson@arm.com port = MasterPort("Port used by the two table walkers") 6010717Sandreas.hansson@arm.com 6110717Sandreas.hansson@arm.com sys = Param.System(Parent.any, "system object parameter") 6210717Sandreas.hansson@arm.com 6312433Sgabeblack@google.comclass ArmTLB(BaseTLB): 646019Shines@cs.fsu.edu type = 'ArmTLB' 656020Sgblack@eecs.umich.edu cxx_class = 'ArmISA::TLB' 669338SAndreas.Sandberg@arm.com cxx_header = "arch/arm/tlb.hh" 6712005Sandreas.sandberg@arm.com sys = Param.System(Parent.any, "system object parameter") 686116Snate@binkert.org size = Param.Int(64, "TLB size") 698756Sgblack@eecs.umich.edu walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") 7010037SARM gem5 Developers is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?") 7110037SARM gem5 Developers 7210037SARM gem5 Developers# Stage 2 translation objects, only used when virtualisation is being used 7310037SARM gem5 Developersclass ArmStage2TableWalker(ArmTableWalker): 7410037SARM gem5 Developers is_stage2 = True 7510037SARM gem5 Developers 7610037SARM gem5 Developersclass ArmStage2TLB(ArmTLB): 7710037SARM gem5 Developers size = 32 7810037SARM gem5 Developers walker = ArmStage2TableWalker() 7910037SARM gem5 Developers is_stage2 = True 8010037SARM gem5 Developers 8110037SARM gem5 Developersclass ArmStage2MMU(SimObject): 8210037SARM gem5 Developers type = 'ArmStage2MMU' 8310037SARM gem5 Developers cxx_class = 'ArmISA::Stage2MMU' 8410037SARM gem5 Developers cxx_header = 'arch/arm/stage2_mmu.hh' 8510037SARM gem5 Developers tlb = Param.ArmTLB("Stage 1 TLB") 8610037SARM gem5 Developers stage2_tlb = Param.ArmTLB("Stage 2 TLB") 8710037SARM gem5 Developers 8810717Sandreas.hansson@arm.com sys = Param.System(Parent.any, "system object parameter") 8910717Sandreas.hansson@arm.com 9010037SARM gem5 Developersclass ArmStage2IMMU(ArmStage2MMU): 9110717Sandreas.hansson@arm.com # We rely on the itb being a parameter of the CPU, and get the 9210717Sandreas.hansson@arm.com # appropriate object that way 9310037SARM gem5 Developers tlb = Parent.itb 9410717Sandreas.hansson@arm.com stage2_tlb = ArmStage2TLB() 9510037SARM gem5 Developers 9610037SARM gem5 Developersclass ArmStage2DMMU(ArmStage2MMU): 9710717Sandreas.hansson@arm.com # We rely on the dtb being a parameter of the CPU, and get the 9810717Sandreas.hansson@arm.com # appropriate object that way 9910037SARM gem5 Developers tlb = Parent.dtb 10010717Sandreas.hansson@arm.com stage2_tlb = ArmStage2TLB() 101