ArmPMU.py revision 13665
12SN/A# -*- mode:python -*- 21762SN/A# Copyright (c) 2009-2014, 2017 ARM Limited 37897Shestness@cs.utexas.edu# All rights reserved. 42SN/A# 52SN/A# The license below extends only to copyright in the software and shall 62SN/A# not be construed as granting a license to any other intellectual 72SN/A# property including but not limited to intellectual property relating 82SN/A# to a hardware implementation of the functionality of the software 92SN/A# licensed hereunder. You may use the software subject to the license 102SN/A# terms below provided that you ensure that this notice is replicated 112SN/A# unmodified and in its entirety in all distributions of the software, 122SN/A# modified or unmodified, in source code or in binary form. 132SN/A# 142SN/A# Redistribution and use in source and binary forms, with or without 152SN/A# modification, are permitted provided that the following conditions are 162SN/A# met: redistributions of source code must retain the above copyright 172SN/A# notice, this list of conditions and the following disclaimer; 182SN/A# redistributions in binary form must reproduce the above copyright 192SN/A# notice, this list of conditions and the following disclaimer in the 202SN/A# documentation and/or other materials provided with the distribution; 212SN/A# neither the name of the copyright holders nor the names of its 222SN/A# contributors may be used to endorse or promote products derived from 232SN/A# this software without specific prior written permission. 242SN/A# 252SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302665Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312665Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327897Shestness@cs.utexas.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362SN/A# 372SN/A# Authors: Matt Horsnell 382SN/A# Andreas Sandberg 3975SN/A 402SN/Afrom m5.defines import buildEnv 412439SN/Afrom m5.SimObject import * 422439SN/Afrom m5.params import * 43603SN/Afrom m5.params import isNullPointer 442986Sgblack@eecs.umich.edufrom m5.proxy import * 45603SN/Afrom m5.objects.Gic import ArmInterruptPin 464762Snate@binkert.org 472520SN/Aclass ProbeEvent(object): 484762Snate@binkert.org def __init__(self, pmu, _eventId, obj, *listOfNames): 492378SN/A self.obj = obj 506658Snate@binkert.org self.names = listOfNames 512378SN/A self.eventId = _eventId 52722SN/A self.pmu = pmu 532378SN/A 54312SN/A def register(self): 551634SN/A if self.obj: 562680Sktlim@umich.edu for name in self.names: 571634SN/A self.pmu.getCCObject().addEventProbe(self.eventId, 582521SN/A self.obj.getCCObject(), name) 592378SN/A 602378SN/Aclass SoftwareIncrement(object): 61803SN/A def __init__(self,pmu, _eventId): 627723SAli.Saidi@ARM.com self.eventId = _eventId 637723SAli.Saidi@ARM.com self.pmu = pmu 643960Sgblack@eecs.umich.edu 652378SN/A def register(self): 666658Snate@binkert.org self.pmu.getCCObject().addSoftwareIncrementEvent(self.eventId) 672SN/A 682SN/AARCH_EVENT_CORE_CYCLES = 0x11 692SN/A 70603SN/Aclass ArmPMU(SimObject): 712901Ssaidi@eecs.umich.edu type = 'ArmPMU' 722902Ssaidi@eecs.umich.edu cxx_class = 'ArmISA::PMU' 732902Ssaidi@eecs.umich.edu cxx_header = 'arch/arm/pmu.hh' 744762Snate@binkert.org 754762Snate@binkert.org cxx_exports = [ 764762Snate@binkert.org PyBindMethod("addEventProbe"), 774762Snate@binkert.org PyBindMethod("addSoftwareIncrementEvent"), 784762Snate@binkert.org ] 794762Snate@binkert.org 802901Ssaidi@eecs.umich.edu _events = None 812901Ssaidi@eecs.umich.edu 822901Ssaidi@eecs.umich.edu def addEvent(self, newObject): 832901Ssaidi@eecs.umich.edu if not (isinstance(newObject, ProbeEvent) 842901Ssaidi@eecs.umich.edu or isinstance(newObject, SoftwareIncrement)): 854762Snate@binkert.org raise TypeError("argument must be of ProbeEvent or " 862901Ssaidi@eecs.umich.edu "SoftwareIncrement type") 872521SN/A 882SN/A if not self._events: 892SN/A self._events = [] 902680Sktlim@umich.edu 915714Shsul@eecs.umich.edu self._events.append(newObject) 921806SN/A 936221Snate@binkert.org # Override the normal SimObject::regProbeListeners method and 945713Shsul@eecs.umich.edu # register deferred event handlers. 955713Shsul@eecs.umich.edu def regProbeListeners(self): 965713Shsul@eecs.umich.edu for event in self._events: 975713Shsul@eecs.umich.edu event.register() 985714Shsul@eecs.umich.edu 991806SN/A self.getCCObject().regProbeListeners() 1006227Snate@binkert.org 1015714Shsul@eecs.umich.edu def addArchEvents(self, 1021806SN/A cpu=None, 103180SN/A itb=None, dtb=None, 1046029Ssteve.reinhardt@amd.com icache=None, dcache=None, 1056029Ssteve.reinhardt@amd.com l2cache=None): 1066029Ssteve.reinhardt@amd.com """Add architected events to the PMU. 1076029Ssteve.reinhardt@amd.com 1088460SAli.Saidi@ARM.com This method can be called multiple times with only a subset of 1098460SAli.Saidi@ARM.com the keyword arguments set. This enables event registration in 1108460SAli.Saidi@ARM.com configuration scripts to happen closer to the instantiation of 1118460SAli.Saidi@ARM.com the instrumented objects (e.g., the memory system) instead of 1128460SAli.Saidi@ARM.com a central point. 1138460SAli.Saidi@ARM.com 1148460SAli.Saidi@ARM.com CPU events should also be registered once per CPU that is 1158460SAli.Saidi@ARM.com sharing the PMU (e.g., when switching between CPU models). 1162378SN/A """ 1172378SN/A 1182378SN/A bpred = getattr(cpu, "branchPred", None) if cpu else None 1192378SN/A if bpred is not None and isNullPointer(bpred): 1202520SN/A bpred = None 1212520SN/A 1227723SAli.Saidi@ARM.com self.addEvent(SoftwareIncrement(self,0x00)) 1237723SAli.Saidi@ARM.com # 0x01: L1I_CACHE_REFILL 1242520SN/A self.addEvent(ProbeEvent(self,0x02, itb, "Refills")) 1251885SN/A # 0x03: L1D_CACHE_REFILL 1261070SN/A # 0x04: L1D_CACHE 127954SN/A self.addEvent(ProbeEvent(self,0x05, dtb, "Refills")) 1281070SN/A self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads")) 1291070SN/A self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores")) 1301070SN/A self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts")) 1311070SN/A # 0x09: EXC_TAKEN 1321070SN/A # 0x0A: EXC_RETURN 1331070SN/A # 0x0B: CID_WRITE_RETIRED 1341070SN/A self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches")) 1351070SN/A # 0x0D: BR_IMMED_RETIRED 1361070SN/A # 0x0E: BR_RETURN_RETIRED 1371070SN/A # 0x0F: UNALIGEND_LDST_RETIRED 1381070SN/A self.addEvent(ProbeEvent(self,0x10, bpred, "Misses")) 1391070SN/A self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu, 1407580SAli.Saidi@arm.com "ActiveCycles")) 1417580SAli.Saidi@arm.com self.addEvent(ProbeEvent(self,0x12, bpred, "Branches")) 1427580SAli.Saidi@arm.com self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads", 1437580SAli.Saidi@arm.com "RetiredStores")) 1447580SAli.Saidi@arm.com # 0x14: L1I_CACHE 1457580SAli.Saidi@arm.com # 0x15: L1D_CACHE_WB 1467580SAli.Saidi@arm.com # 0x16: L2D_CACHE 1477580SAli.Saidi@arm.com # 0x17: L2D_CACHE_REFILL 1482378SN/A # 0x18: L2D_CACHE_WB 1492378SN/A # 0x19: BUS_ACCESS 1507770SAli.Saidi@ARM.com # 0x1A: MEMORY_ERROR 1512378SN/A # 0x1B: INST_SPEC 1524997Sgblack@eecs.umich.edu # 0x1C: TTBR_WRITE_RETIRED 1537770SAli.Saidi@ARM.com # 0x1D: BUS_CYCLES 1544997Sgblack@eecs.umich.edu # 0x1E: CHAIN 1554997Sgblack@eecs.umich.edu # 0x1F: L1D_CACHE_ALLOCATE 1564997Sgblack@eecs.umich.edu # 0x20: L2D_CACHE_ALLOCATE 1574997Sgblack@eecs.umich.edu # 0x21: BR_RETIRED 1587770SAli.Saidi@ARM.com # 0x22: BR_MIS_PRED_RETIRED 1594997Sgblack@eecs.umich.edu # 0x23: STALL_FRONTEND 1604997Sgblack@eecs.umich.edu # 0x24: STALL_BACKEND 1615795Ssaidi@eecs.umich.edu # 0x25: L1D_TLB 1625795Ssaidi@eecs.umich.edu # 0x26: L1I_TLB 1635795Ssaidi@eecs.umich.edu # 0x27: L2I_CACHE 1645795Ssaidi@eecs.umich.edu # 0x28: L2I_CACHE_REFILL 1655795Ssaidi@eecs.umich.edu # 0x29: L3D_CACHE_ALLOCATE 1665795Ssaidi@eecs.umich.edu # 0x2A: L3D_CACHE_REFILL 1672378SN/A # 0x2B: L3D_CACHE 1682378SN/A # 0x2C: L3D_CACHE_WB 1692378SN/A # 0x2D: L2D_TLB_REFILL 1701885SN/A # 0x2E: L2I_TLB_REFILL 1714762Snate@binkert.org # 0x2F: L2D_TLB 1727914SBrad.Beckmann@amd.com # 0x30: L2I_TLB 1737914SBrad.Beckmann@amd.com 1747914SBrad.Beckmann@amd.com cycleEventId = Param.Int(ARCH_EVENT_CORE_CYCLES, "Cycle event id") 1757914SBrad.Beckmann@amd.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 1767914SBrad.Beckmann@amd.com eventCounters = Param.Int(31, "Number of supported PMU counters") 1777914SBrad.Beckmann@amd.com interrupt = Param.ArmInterruptPin("PMU interrupt") 1787914SBrad.Beckmann@amd.com