ArmISA.py revision 9385:25ebe5e13a07
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
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15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
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24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Andreas Sandberg
37
38from m5.params import *
39from m5.SimObject import SimObject
40
41class ArmISA(SimObject):
42    type = 'ArmISA'
43    cxx_class = 'ArmISA::ISA'
44    cxx_header = "arch/arm/isa.hh"
45
46    # 0x35 Implementor is '5' from "M5"
47    # 0x0 Variant
48    # 0xf Architecture from CPUID scheme
49    # 0xc00 Primary part number ("c" or higher implies ARM v7)
50    # 0x0 Revision
51    midr = Param.UInt32(0x350fc000, "Main ID Register")
52
53    # See section B4.1.93 - B4.1.94 of the ARM ARM
54    #
55    # !ThumbEE | !Jazelle | Thumb | ARM
56    # Note: ThumbEE is disabled for now since we don't support CP14
57    # config registers and jumping to ThumbEE vectors
58    id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
59    # !Timer | !Virti | !M Profile | !TrustZone | ARMv4
60    id_pfr1 = Param.UInt32(0x00000001, "Processor Feature Register 1")
61
62    # See section B4.1.89 - B4.1.92 of the ARM ARM
63    #  VMSAv7 support
64    id_mmfr0 = Param.UInt32(0x00000003, "Memory Model Feature Register 0")
65    id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
66    # no HW access | WFI stalling | ISB and DSB |
67    # all TLB maintenance | no Harvard
68    id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
69    # SuperSec | Coherent TLB | Bcast Maint |
70    # BP Maint | Cache Maint Set/way | Cache Maint MVA
71    id_mmfr3 = Param.UInt32(0xF0102211, "Memory Model Feature Register 3")
72
73    # See section B4.1.84 of ARM ARM
74    # All values are latest for ARMv7-A profile
75    id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
76    id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
77    id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
78    id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
79    id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
80    id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
81
82
83    fpsid = Param.UInt32(0x410430A0, "Floating-point System ID Register")
84