ArmISA.py revision 10461:afeb5cdb3907
16019Shines@cs.fsu.edu# Copyright (c) 2012-2013 ARM Limited 27093Sgblack@eecs.umich.edu# All rights reserved. 37093Sgblack@eecs.umich.edu# 47093Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 57093Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 67093Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 77093Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 87093Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 97093Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 107093Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 117093Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 127093Sgblack@eecs.umich.edu# 137093Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 146019Shines@cs.fsu.edu# modification, are permitted provided that the following conditions are 156019Shines@cs.fsu.edu# met: redistributions of source code must retain the above copyright 166019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer; 176019Shines@cs.fsu.edu# redistributions in binary form must reproduce the above copyright 186019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer in the 196019Shines@cs.fsu.edu# documentation and/or other materials provided with the distribution; 206019Shines@cs.fsu.edu# neither the name of the copyright holders nor the names of its 216019Shines@cs.fsu.edu# contributors may be used to endorse or promote products derived from 226019Shines@cs.fsu.edu# this software without specific prior written permission. 236019Shines@cs.fsu.edu# 246019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 256019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 266019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 276019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 286019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 296019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 306019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 316019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 326019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 336019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 346019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 356019Shines@cs.fsu.edu# 366019Shines@cs.fsu.edu# Authors: Andreas Sandberg 376019Shines@cs.fsu.edu# Giacomo Gabrielli 386019Shines@cs.fsu.edu 396019Shines@cs.fsu.edufrom m5.params import * 407399SAli.Saidi@ARM.comfrom m5.proxy import * 417399SAli.Saidi@ARM.comfrom m5.SimObject import SimObject 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edufrom ArmPMU import ArmPMU 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.educlass ArmISA(SimObject): 466019Shines@cs.fsu.edu type = 'ArmISA' 476019Shines@cs.fsu.edu cxx_class = 'ArmISA::ISA' 486116Snate@binkert.org cxx_header = "arch/arm/isa.hh" 496019Shines@cs.fsu.edu 506019Shines@cs.fsu.edu system = Param.System(Parent.any, "System this ISA object belongs to") 516019Shines@cs.fsu.edu 526019Shines@cs.fsu.edu pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit") 536019Shines@cs.fsu.edu 546019Shines@cs.fsu.edu midr = Param.UInt32(0x410fc0f0, "MIDR value") 556019Shines@cs.fsu.edu 566116Snate@binkert.org # See section B4.1.93 - B4.1.94 of the ARM ARM 576116Snate@binkert.org # 586019Shines@cs.fsu.edu # !ThumbEE | !Jazelle | Thumb | ARM 596019Shines@cs.fsu.edu # Note: ThumbEE is disabled for now since we don't support CP14 607406SAli.Saidi@ARM.com # config registers and jumping to ThumbEE vectors 617406SAli.Saidi@ARM.com id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0") 627406SAli.Saidi@ARM.com # !Timer | Virti | !M Profile | TrustZone | ARMv4 637406SAli.Saidi@ARM.com id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1") 646019Shines@cs.fsu.edu 656019Shines@cs.fsu.edu # See section B4.1.89 - B4.1.92 of the ARM ARM 666019Shines@cs.fsu.edu # VMSAv7 support 676019Shines@cs.fsu.edu id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0") 687697SAli.Saidi@ARM.com id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1") 697404SAli.Saidi@ARM.com # no HW access | WFI stalling | ISB and DSB | 707404SAli.Saidi@ARM.com # all TLB maintenance | no Harvard 717404SAli.Saidi@ARM.com id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2") 727749SAli.Saidi@ARM.com # SuperSec | Coherent TLB | Bcast Maint | 736019Shines@cs.fsu.edu # BP Maint | Cache Maint Set/way | Cache Maint MVA 747404SAli.Saidi@ARM.com id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3") 757404SAli.Saidi@ARM.com 767399SAli.Saidi@ARM.com # See section B4.1.84 of ARM ARM 777406SAli.Saidi@ARM.com # All values are latest for ARMv7-A profile 787404SAli.Saidi@ARM.com id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0") 797406SAli.Saidi@ARM.com id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1") 806019Shines@cs.fsu.edu id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2") 816019Shines@cs.fsu.edu id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3") 826019Shines@cs.fsu.edu id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4") 836019Shines@cs.fsu.edu id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5") 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.edu fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register") 866019Shines@cs.fsu.edu 876019Shines@cs.fsu.edu # [31:0] is implementation defined 887694SAli.Saidi@ARM.com id_aa64afr0_el1 = Param.UInt64(0x0000000000000000, 897694SAli.Saidi@ARM.com "AArch64 Auxiliary Feature Register 0") 907694SAli.Saidi@ARM.com # Reserved for future expansion 917749SAli.Saidi@ARM.com id_aa64afr1_el1 = Param.UInt64(0x0000000000000000, 927749SAli.Saidi@ARM.com "AArch64 Auxiliary Feature Register 1") 937749SAli.Saidi@ARM.com 947694SAli.Saidi@ARM.com # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A 957694SAli.Saidi@ARM.com id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006, 967694SAli.Saidi@ARM.com "AArch64 Debug Feature Register 0") 977694SAli.Saidi@ARM.com # Reserved for future expansion 987694SAli.Saidi@ARM.com id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000, 997694SAli.Saidi@ARM.com "AArch64 Debug Feature Register 1") 1007404SAli.Saidi@ARM.com 1017694SAli.Saidi@ARM.com # !CRC32 | !SHA2 | !SHA1 | !AES 1026019Shines@cs.fsu.edu id_aa64isar0_el1 = Param.UInt64(0x0000000000000000, 1037404SAli.Saidi@ARM.com "AArch64 Instruction Set Attribute Register 0") 1047404SAli.Saidi@ARM.com # Reserved for future expansion 1057404SAli.Saidi@ARM.com id_aa64isar1_el1 = Param.UInt64(0x0000000000000000, 1067697SAli.Saidi@ARM.com "AArch64 Instruction Set Attribute Register 1") 1077404SAli.Saidi@ARM.com 1087404SAli.Saidi@ARM.com # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA 1097404SAli.Saidi@ARM.com id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002, 1107404SAli.Saidi@ARM.com "AArch64 Memory Model Feature Register 0") 1117404SAli.Saidi@ARM.com # Reserved for future expansion 1127697SAli.Saidi@ARM.com id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000, 1137697SAli.Saidi@ARM.com "AArch64 Memory Model Feature Register 1") 1147697SAli.Saidi@ARM.com 1157697SAli.Saidi@ARM.com # !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64) 1167697SAli.Saidi@ARM.com # (no AArch32/64 interprocessing support for now) 1177697SAli.Saidi@ARM.com id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011, 1187697SAli.Saidi@ARM.com "AArch64 Processor Feature Register 0") 1197697SAli.Saidi@ARM.com # Reserved for future expansion 1207697SAli.Saidi@ARM.com id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000, 1217697SAli.Saidi@ARM.com "AArch64 Processor Feature Register 1") 1227404SAli.Saidi@ARM.com