vtophys.cc revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <string>
30
31#include "arch/alpha/ev5.hh"
32#include "arch/alpha/vtophys.hh"
33#include "base/chunk_generator.hh"
34#include "base/trace.hh"
35#include "cpu/exec_context.hh"
36#include "mem/vport.hh"
37
38using namespace std;
39using namespace AlphaISA;
40
41AlphaISA::PageTableEntry
42AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
43{
44    Addr level1_pte = ptbr + vaddr.level1();
45    AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
46    if (!level1.valid()) {
47        DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
48        return 0;
49    }
50
51    Addr level2_pte = level1.paddr() + vaddr.level2();
52    AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
53    if (!level2.valid()) {
54        DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
55        return 0;
56    }
57
58    Addr level3_pte = level2.paddr() + vaddr.level3();
59    AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
60    if (!level3.valid()) {
61        DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
62        return 0;
63    }
64    return level3;
65}
66
67Addr
68AlphaISA::vtophys(Addr vaddr)
69{
70    Addr paddr = 0;
71    if (AlphaISA::IsUSeg(vaddr))
72        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
73    else if (AlphaISA::IsK0Seg(vaddr))
74        paddr = AlphaISA::K0Seg2Phys(vaddr);
75    else
76        panic("vtophys: ptbr is not set on virtual lookup");
77
78    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
79
80    return paddr;
81}
82
83Addr
84AlphaISA::vtophys(ExecContext *xc, Addr addr)
85{
86    AlphaISA::VAddr vaddr = addr;
87    Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
88    Addr paddr = 0;
89    //@todo Andrew couldn't remember why he commented some of this code
90    //so I put it back in. Perhaps something to do with gdb debugging?
91    if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
92        paddr = vaddr & ~ULL(1);
93    } else {
94        if (AlphaISA::IsK0Seg(vaddr)) {
95            paddr = AlphaISA::K0Seg2Phys(vaddr);
96        } else if (!ptbr) {
97            paddr = vaddr;
98        } else {
99            AlphaISA::PageTableEntry pte =
100                kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr);
101            if (pte.valid())
102                paddr = pte.paddr() | vaddr.offset();
103        }
104    }
105
106
107    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
108
109    return paddr;
110}
111
112
113void
114AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
115{
116    uint8_t *dst = (uint8_t *)dest;
117    VirtualPort *vp = xc->getVirtPort(xc);
118
119    vp->readBlob(src, dst, cplen);
120
121    xc->delVirtPort(vp);
122
123}
124
125void
126AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
127{
128    uint8_t *src = (uint8_t *)source;
129    VirtualPort *vp = xc->getVirtPort(xc);
130
131    vp->writeBlob(dest, src, cplen);
132
133    xc->delVirtPort(vp);
134}
135
136void
137AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
138{
139    int len = 0;
140    VirtualPort *vp = xc->getVirtPort(xc);
141
142    do {
143        vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
144        len++;
145    } while (len < maxlen && dst[len] != 0 );
146
147    xc->delVirtPort(vp);
148    dst[len] = 0;
149}
150
151void
152AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr)
153{
154    VirtualPort *vp = xc->getVirtPort(xc);
155    for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
156            gen.next())
157    {
158        vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
159        src += gen.size();
160    }
161    xc->delVirtPort(vp);
162}
163