vtophys.cc revision 11793
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert
292665Ssaidi@eecs.umich.edu *          Steve Reinhardt
302665Ssaidi@eecs.umich.edu *          Ali Saidi
312SN/A */
322SN/A
3311793Sbrandon.potter@amd.com#include "arch/alpha/vtophys.hh"
3411793Sbrandon.potter@amd.com
352SN/A#include <string>
362SN/A
372521SN/A#include "arch/alpha/ev5.hh"
382521SN/A#include "base/chunk_generator.hh"
391110SN/A#include "base/trace.hh"
402680Sktlim@umich.edu#include "cpu/thread_context.hh"
418232Snate@binkert.org#include "debug/VtoPhys.hh"
428706Sandreas.hansson@arm.com#include "mem/port_proxy.hh"
432SN/A
442SN/Ausing namespace std;
452SN/A
465568Snate@binkert.orgnamespace AlphaISA {
475568Snate@binkert.org
485568Snate@binkert.orgPageTableEntry
498852Sandreas.hansson@arm.comkernel_pte_lookup(PortProxy &mem, Addr ptbr, VAddr vaddr)
502SN/A{
511111SN/A    Addr level1_pte = ptbr + vaddr.level1();
528852Sandreas.hansson@arm.com    PageTableEntry level1 = mem.read<uint64_t>(level1_pte);
531111SN/A    if (!level1.valid()) {
542SN/A        DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
552SN/A        return 0;
562SN/A    }
572SN/A
581111SN/A    Addr level2_pte = level1.paddr() + vaddr.level2();
598852Sandreas.hansson@arm.com    PageTableEntry level2 = mem.read<uint64_t>(level2_pte);
601111SN/A    if (!level2.valid()) {
612SN/A        DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
622SN/A        return 0;
632SN/A    }
642SN/A
651111SN/A    Addr level3_pte = level2.paddr() + vaddr.level3();
668852Sandreas.hansson@arm.com    PageTableEntry level3 = mem.read<uint64_t>(level3_pte);
671111SN/A    if (!level3.valid()) {
681111SN/A        DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
691111SN/A        return 0;
701111SN/A    }
711111SN/A    return level3;
722SN/A}
732SN/A
742SN/AAddr
755568Snate@binkert.orgvtophys(Addr vaddr)
762SN/A{
772SN/A    Addr paddr = 0;
785568Snate@binkert.org    if (IsUSeg(vaddr))
792SN/A        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
805568Snate@binkert.org    else if (IsK0Seg(vaddr))
815568Snate@binkert.org        paddr = K0Seg2Phys(vaddr);
822SN/A    else
832SN/A        panic("vtophys: ptbr is not set on virtual lookup");
842SN/A
852SN/A    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
862SN/A
872SN/A    return paddr;
882SN/A}
892SN/A
902SN/AAddr
915568Snate@binkert.orgvtophys(ThreadContext *tc, Addr addr)
922SN/A{
935568Snate@binkert.org    VAddr vaddr = addr;
945568Snate@binkert.org    Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
952SN/A    Addr paddr = 0;
96924SN/A    //@todo Andrew couldn't remember why he commented some of this code
97924SN/A    //so I put it back in. Perhaps something to do with gdb debugging?
985568Snate@binkert.org    if (PcPAL(vaddr) && (vaddr < PalMax)) {
99924SN/A        paddr = vaddr & ~ULL(1);
100924SN/A    } else {
1015568Snate@binkert.org        if (IsK0Seg(vaddr)) {
1025568Snate@binkert.org            paddr = K0Seg2Phys(vaddr);
103973SN/A        } else if (!ptbr) {
104973SN/A            paddr = vaddr;
105547SN/A        } else {
1065568Snate@binkert.org            PageTableEntry pte =
1078706Sandreas.hansson@arm.com                kernel_pte_lookup(tc->getPhysProxy(), ptbr, vaddr);
1081111SN/A            if (pte.valid())
1091111SN/A                paddr = pte.paddr() | vaddr.offset();
110547SN/A        }
111924SN/A    }
112924SN/A
1132SN/A
1142SN/A    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
1152SN/A
1162SN/A    return paddr;
1172SN/A}
1182SN/A
1195568Snate@binkert.org} // namespace AlphaISA
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