utility.hh revision 7707:e5b6f1157be3 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "arch/alpha/types.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "arch/alpha/registers.hh"
38#include "base/misc.hh"
39#include "config/full_system.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA {
43
44uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
45
46inline bool
47inUserMode(ThreadContext *tc)
48{
49    return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
50}
51
52/**
53 * Function to insure ISA semantics about 0 registers.
54 * @param tc The thread context.
55 */
56template <class TC>
57void zeroRegisters(TC *tc);
58
59// Alpha IPR register accessors
60inline bool PcPAL(Addr addr) { return addr & 0x3; }
61inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
62
63////////////////////////////////////////////////////////////////////////
64//
65//  Translation stuff
66//
67
68inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
69
70// User Virtual
71inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
72
73// Kernel Direct Mapped
74inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
75inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
76
77// Kernel Virtual
78inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
79
80inline Addr
81TruncPage(Addr addr)
82{ return addr & ~(PageBytes - 1); }
83
84inline Addr
85RoundPage(Addr addr)
86{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
87
88void initIPRs(ThreadContext *tc, int cpuId);
89#if FULL_SYSTEM
90void initCPU(ThreadContext *tc, int cpuId);
91#endif
92
93void copyRegs(ThreadContext *src, ThreadContext *dest);
94
95void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
96
97void skipFunction(ThreadContext *tc);
98} // namespace AlphaISA
99
100#endif // __ARCH_ALPHA_UTILITY_HH__
101