utility.hh revision 6325:7a020652cd85 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "arch/alpha/types.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "arch/alpha/regfile.hh"
38#include "base/misc.hh"
39#include "config/full_system.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA {
43
44uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46inline bool
47inUserMode(ThreadContext *tc)
48{
49    return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
50}
51
52inline bool
53isCallerSaveIntegerRegister(unsigned int reg)
54{
55    panic("register classification not implemented");
56    return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
57}
58
59inline bool
60isCalleeSaveIntegerRegister(unsigned int reg)
61{
62    panic("register classification not implemented");
63    return reg >= 9 && reg <= 15;
64}
65
66inline bool
67isCallerSaveFloatRegister(unsigned int reg)
68{
69    panic("register classification not implemented");
70    return false;
71}
72
73inline bool
74isCalleeSaveFloatRegister(unsigned int reg)
75{
76    panic("register classification not implemented");
77    return false;
78}
79
80inline Addr
81alignAddress(const Addr &addr, unsigned int nbytes)
82{
83    return (addr & ~(nbytes - 1));
84}
85
86// Instruction address compression hooks
87inline Addr
88realPCToFetchPC(const Addr &addr)
89{
90    return addr;
91}
92
93inline Addr
94fetchPCToRealPC(const Addr &addr)
95{
96    return addr;
97}
98
99// the size of "fetched" instructions (not necessarily the size
100// of real instructions for PISA)
101inline size_t
102fetchInstSize()
103{
104    return sizeof(MachInst);
105}
106
107inline MachInst
108makeRegisterCopy(int dest, int src)
109{
110    panic("makeRegisterCopy not implemented");
111    return 0;
112}
113
114/**
115 * Function to insure ISA semantics about 0 registers.
116 * @param tc The thread context.
117 */
118template <class TC>
119void zeroRegisters(TC *tc);
120
121// Alpha IPR register accessors
122inline bool PcPAL(Addr addr) { return addr & 0x3; }
123inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
124
125////////////////////////////////////////////////////////////////////////
126//
127//  Translation stuff
128//
129
130inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
131
132// User Virtual
133inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
134
135// Kernel Direct Mapped
136inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
137inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
138
139// Kernel Virtual
140inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
141
142inline Addr
143TruncPage(Addr addr)
144{ return addr & ~(PageBytes - 1); }
145
146inline Addr
147RoundPage(Addr addr)
148{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
149
150void initIPRs(ThreadContext *tc, int cpuId);
151#if FULL_SYSTEM
152void initCPU(ThreadContext *tc, int cpuId);
153
154/**
155 * Function to check for and process any interrupts.
156 * @param tc The thread context.
157 */
158template <class TC>
159void processInterrupts(TC *tc);
160#endif
161
162} // namespace AlphaISA
163
164#endif // __ARCH_ALPHA_UTILITY_HH__
165