utility.hh revision 8229
12440SN/A/* 22440SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302440SN/A */ 312440SN/A 322440SN/A#ifndef __ARCH_ALPHA_UTILITY_HH__ 332440SN/A#define __ARCH_ALPHA_UTILITY_HH__ 342440SN/A 352972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 366330Sgblack@eecs.umich.edu#include "arch/alpha/registers.hh" 378229Snate@binkert.org#include "arch/alpha/types.hh" 382440SN/A#include "base/misc.hh" 395569Snate@binkert.org#include "config/full_system.hh" 407720Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 413120Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 422440SN/A 435569Snate@binkert.orgnamespace AlphaISA { 445569Snate@binkert.org 457720Sgblack@eecs.umich.eduinline PCState 467720Sgblack@eecs.umich.edubuildRetPC(const PCState &curPC, const PCState &callPC) 477720Sgblack@eecs.umich.edu{ 487720Sgblack@eecs.umich.edu PCState retPC = callPC; 497720Sgblack@eecs.umich.edu retPC.advance(); 507720Sgblack@eecs.umich.edu return retPC; 517720Sgblack@eecs.umich.edu} 527720Sgblack@eecs.umich.edu 537707Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 545569Snate@binkert.org 555569Snate@binkert.orginline bool 565569Snate@binkert.orginUserMode(ThreadContext *tc) 572440SN/A{ 585569Snate@binkert.org return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 595569Snate@binkert.org} 604826Ssaidi@eecs.umich.edu 615569Snate@binkert.org/** 625569Snate@binkert.org * Function to insure ISA semantics about 0 registers. 635569Snate@binkert.org * @param tc The thread context. 645569Snate@binkert.org */ 655569Snate@binkert.orgtemplate <class TC> 665569Snate@binkert.orgvoid zeroRegisters(TC *tc); 672440SN/A 685569Snate@binkert.org// Alpha IPR register accessors 695569Snate@binkert.orginline bool PcPAL(Addr addr) { return addr & 0x3; } 705569Snate@binkert.orginline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 712440SN/A 725569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 735569Snate@binkert.org// 745569Snate@binkert.org// Translation stuff 755569Snate@binkert.org// 762440SN/A 775569Snate@binkert.orginline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 782440SN/A 795569Snate@binkert.org// User Virtual 805569Snate@binkert.orginline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 812440SN/A 825569Snate@binkert.org// Kernel Direct Mapped 835569Snate@binkert.orginline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 845569Snate@binkert.orginline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 852440SN/A 865569Snate@binkert.org// Kernel Virtual 875569Snate@binkert.orginline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 882440SN/A 895569Snate@binkert.orginline Addr 905569Snate@binkert.orgTruncPage(Addr addr) 915569Snate@binkert.org{ return addr & ~(PageBytes - 1); } 922440SN/A 935569Snate@binkert.orginline Addr 945569Snate@binkert.orgRoundPage(Addr addr) 955569Snate@binkert.org{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 962440SN/A 975569Snate@binkert.orgvoid initIPRs(ThreadContext *tc, int cpuId); 985569Snate@binkert.org#if FULL_SYSTEM 995569Snate@binkert.orgvoid initCPU(ThreadContext *tc, int cpuId); 1002440SN/A#endif 1012440SN/A 1026329Sgblack@eecs.umich.eduvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1036329Sgblack@eecs.umich.edu 1046329Sgblack@eecs.umich.eduvoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1056329Sgblack@eecs.umich.edu 1067693SAli.Saidi@ARM.comvoid skipFunction(ThreadContext *tc); 1077720Sgblack@eecs.umich.edu 1087720Sgblack@eecs.umich.eduinline void 1097720Sgblack@eecs.umich.eduadvancePC(PCState &pc, const StaticInstPtr inst) 1107720Sgblack@eecs.umich.edu{ 1117720Sgblack@eecs.umich.edu pc.advance(); 1127720Sgblack@eecs.umich.edu} 1137720Sgblack@eecs.umich.edu 1142440SN/A} // namespace AlphaISA 1152440SN/A 1165569Snate@binkert.org#endif // __ARCH_ALPHA_UTILITY_HH__ 117