utility.hh revision 7720
12124SN/A/* 22124SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu * 285268Sksewell@umich.edu * Authors: Nathan Binkert 295268Sksewell@umich.edu * Steve Reinhardt 305268Sksewell@umich.edu */ 312022SN/A 322649Ssaidi@eecs.umich.edu#ifndef __ARCH_ALPHA_UTILITY_HH__ 332649Ssaidi@eecs.umich.edu#define __ARCH_ALPHA_UTILITY_HH__ 342706Sksewell@umich.edu 352649Ssaidi@eecs.umich.edu#include "arch/alpha/types.hh" 362649Ssaidi@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 372022SN/A#include "arch/alpha/registers.hh" 382124SN/A#include "base/misc.hh" 392124SN/A#include "config/full_system.hh" 402124SN/A#include "cpu/static_inst.hh" 412124SN/A#include "cpu/thread_context.hh" 422124SN/A 432124SN/Anamespace AlphaISA { 442124SN/A 455736Snate@binkert.orginline PCState 462239SN/AbuildRetPC(const PCState &curPC, const PCState &callPC) 472124SN/A{ 482124SN/A PCState retPC = callPC; 492124SN/A retPC.advance(); 502124SN/A return retPC; 516207Sksewell@umich.edu} 522124SN/A 532742Sksewell@umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 542022SN/A 552124SN/Ainline bool 562022SN/AinUserMode(ThreadContext *tc) 572124SN/A{ 582124SN/A return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 592124SN/A} 602124SN/A 612742Sksewell@umich.edu/** 622742Sksewell@umich.edu * Function to insure ISA semantics about 0 registers. 632742Sksewell@umich.edu * @param tc The thread context. 642742Sksewell@umich.edu */ 652742Sksewell@umich.edutemplate <class TC> 662742Sksewell@umich.eduvoid zeroRegisters(TC *tc); 672742Sksewell@umich.edu 682742Sksewell@umich.edu// Alpha IPR register accessors 696207Sksewell@umich.eduinline bool PcPAL(Addr addr) { return addr & 0x3; } 706207Sksewell@umich.eduinline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 712742Sksewell@umich.edu 722742Sksewell@umich.edu//////////////////////////////////////////////////////////////////////// 732742Sksewell@umich.edu// 742742Sksewell@umich.edu// Translation stuff 752742Sksewell@umich.edu// 762742Sksewell@umich.edu 772022SN/Ainline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 782022SN/A 792124SN/A// User Virtual 802022SN/Ainline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 812124SN/A 822124SN/A// Kernel Direct Mapped 832124SN/Ainline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 842742Sksewell@umich.eduinline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 852239SN/A 862124SN/A// Kernel Virtual 872124SN/Ainline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 882742Sksewell@umich.edu 892742Sksewell@umich.eduinline Addr 902742Sksewell@umich.eduTruncPage(Addr addr) 912742Sksewell@umich.edu{ return addr & ~(PageBytes - 1); } 922742Sksewell@umich.edu 932742Sksewell@umich.eduinline Addr 942742Sksewell@umich.eduRoundPage(Addr addr) 952742Sksewell@umich.edu{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 964661Sksewell@umich.edu 974661Sksewell@umich.eduvoid initIPRs(ThreadContext *tc, int cpuId); 984661Sksewell@umich.edu#if FULL_SYSTEM 994661Sksewell@umich.eduvoid initCPU(ThreadContext *tc, int cpuId); 1004661Sksewell@umich.edu#endif 1014661Sksewell@umich.edu 1024661Sksewell@umich.eduvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1035222Sksewell@umich.edu 1044661Sksewell@umich.eduvoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1054661Sksewell@umich.edu 1065222Sksewell@umich.eduvoid skipFunction(ThreadContext *tc); 1074661Sksewell@umich.edu 1084661Sksewell@umich.eduinline void 1095222Sksewell@umich.eduadvancePC(PCState &pc, const StaticInstPtr inst) 1104661Sksewell@umich.edu{ 1114661Sksewell@umich.edu pc.advance(); 1125222Sksewell@umich.edu} 1134661Sksewell@umich.edu 1144661Sksewell@umich.edu} // namespace AlphaISA 1155222Sksewell@umich.edu 1164661Sksewell@umich.edu#endif // __ARCH_ALPHA_UTILITY_HH__ 1174661Sksewell@umich.edu