utility.hh revision 7707 
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2711723Sar4jc@virginia.edu *
2811723Sar4jc@virginia.edu * Authors: Nathan Binkert
2911723Sar4jc@virginia.edu *          Steve Reinhardt
3011723Sar4jc@virginia.edu */
3111723Sar4jc@virginia.edu
3211723Sar4jc@virginia.edu#ifndef __ARCH_ALPHA_UTILITY_HH__
3311723Sar4jc@virginia.edu#define __ARCH_ALPHA_UTILITY_HH__
3411723Sar4jc@virginia.edu
3511723Sar4jc@virginia.edu#include "arch/alpha/types.hh"
3611723Sar4jc@virginia.edu#include "arch/alpha/isa_traits.hh"
3711723Sar4jc@virginia.edu#include "arch/alpha/registers.hh"
3811723Sar4jc@virginia.edu#include "base/misc.hh"
3911723Sar4jc@virginia.edu#include "config/full_system.hh"
4011723Sar4jc@virginia.edu#include "cpu/thread_context.hh"
4111723Sar4jc@virginia.edu
4211723Sar4jc@virginia.edunamespace AlphaISA {
4311723Sar4jc@virginia.edu
4411723Sar4jc@virginia.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
4511723Sar4jc@virginia.edu
4611723Sar4jc@virginia.eduinline bool
4711723Sar4jc@virginia.eduinUserMode(ThreadContext *tc)
4811723Sar4jc@virginia.edu{
4911723Sar4jc@virginia.edu    return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
5011723Sar4jc@virginia.edu}
5111723Sar4jc@virginia.edu
5211723Sar4jc@virginia.edu/**
5311723Sar4jc@virginia.edu * Function to insure ISA semantics about 0 registers.
5411723Sar4jc@virginia.edu * @param tc The thread context.
55 */
56template <class TC>
57void zeroRegisters(TC *tc);
58
59// Alpha IPR register accessors
60inline bool PcPAL(Addr addr) { return addr & 0x3; }
61inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
62
63////////////////////////////////////////////////////////////////////////
64//
65//  Translation stuff
66//
67
68inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
69
70// User Virtual
71inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
72
73// Kernel Direct Mapped
74inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
75inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
76
77// Kernel Virtual
78inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
79
80inline Addr
81TruncPage(Addr addr)
82{ return addr & ~(PageBytes - 1); }
83
84inline Addr
85RoundPage(Addr addr)
86{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
87
88void initIPRs(ThreadContext *tc, int cpuId);
89#if FULL_SYSTEM
90void initCPU(ThreadContext *tc, int cpuId);
91#endif
92
93void copyRegs(ThreadContext *src, ThreadContext *dest);
94
95void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
96
97void skipFunction(ThreadContext *tc);
98} // namespace AlphaISA
99
100#endif // __ARCH_ALPHA_UTILITY_HH__
101