utility.hh revision 6329
12381SN/A/* 22381SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32381SN/A * All rights reserved. 42381SN/A * 52381SN/A * Redistribution and use in source and binary forms, with or without 62381SN/A * modification, are permitted provided that the following conditions are 72381SN/A * met: redistributions of source code must retain the above copyright 82381SN/A * notice, this list of conditions and the following disclaimer; 92381SN/A * redistributions in binary form must reproduce the above copyright 102381SN/A * notice, this list of conditions and the following disclaimer in the 112381SN/A * documentation and/or other materials provided with the distribution; 122381SN/A * neither the name of the copyright holders nor the names of its 132381SN/A * contributors may be used to endorse or promote products derived from 142381SN/A * this software without specific prior written permission. 152381SN/A * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272381SN/A * 282381SN/A * Authors: Nathan Binkert 292381SN/A * Steve Reinhardt 302381SN/A */ 312381SN/A 322381SN/A#ifndef __ARCH_ALPHA_UTILITY_HH__ 332381SN/A#define __ARCH_ALPHA_UTILITY_HH__ 342381SN/A 352381SN/A#include "arch/alpha/types.hh" 362381SN/A#include "arch/alpha/isa_traits.hh" 372381SN/A#include "arch/alpha/miscregfile.hh" 382381SN/A#include "base/misc.hh" 392381SN/A#include "config/full_system.hh" 402381SN/A#include "cpu/thread_context.hh" 412381SN/A 422381SN/Anamespace AlphaISA { 432381SN/A 442439SN/Auint64_t getArgument(ThreadContext *tc, int number, bool fp); 452381SN/A 462381SN/Ainline bool 472381SN/AinUserMode(ThreadContext *tc) 482381SN/A{ 492407SN/A return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 502407SN/A} 512407SN/A 522407SN/Ainline bool 532407SN/AisCallerSaveIntegerRegister(unsigned int reg) 542407SN/A{ 552407SN/A panic("register classification not implemented"); 562407SN/A return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27; 572521SN/A} 582407SN/A 592381SN/Ainline bool 602381SN/AisCalleeSaveIntegerRegister(unsigned int reg) 612381SN/A{ 622381SN/A panic("register classification not implemented"); 632381SN/A return reg >= 9 && reg <= 15; 642381SN/A} 652381SN/A 662381SN/Ainline bool 672381SN/AisCallerSaveFloatRegister(unsigned int reg) 682381SN/A{ 692381SN/A panic("register classification not implemented"); 702381SN/A return false; 712381SN/A} 722640Sstever@eecs.umich.edu 732640Sstever@eecs.umich.eduinline bool 742640Sstever@eecs.umich.eduisCalleeSaveFloatRegister(unsigned int reg) 752640Sstever@eecs.umich.edu{ 762640Sstever@eecs.umich.edu panic("register classification not implemented"); 772661Sstever@eecs.umich.edu return false; 782661Sstever@eecs.umich.edu} 792661Sstever@eecs.umich.edu 802661Sstever@eecs.umich.eduinline Addr 812661Sstever@eecs.umich.edualignAddress(const Addr &addr, unsigned int nbytes) 822381SN/A{ 832381SN/A return (addr & ~(nbytes - 1)); 842640Sstever@eecs.umich.edu} 852640Sstever@eecs.umich.edu 862640Sstever@eecs.umich.edu// Instruction address compression hooks 872640Sstever@eecs.umich.eduinline Addr 882640Sstever@eecs.umich.edurealPCToFetchPC(const Addr &addr) 892640Sstever@eecs.umich.edu{ 902640Sstever@eecs.umich.edu return addr; 912661Sstever@eecs.umich.edu} 922640Sstever@eecs.umich.edu 932640Sstever@eecs.umich.eduinline Addr 942640Sstever@eecs.umich.edufetchPCToRealPC(const Addr &addr) 952640Sstever@eecs.umich.edu{ 962640Sstever@eecs.umich.edu return addr; 972474SN/A} 982640Sstever@eecs.umich.edu 992381SN/A// the size of "fetched" instructions (not necessarily the size 1002657Ssaidi@eecs.umich.edu// of real instructions for PISA) 1012657Ssaidi@eecs.umich.eduinline size_t 1022381SN/AfetchInstSize() 1032381SN/A{ 1042381SN/A return sizeof(MachInst); 1052381SN/A} 1062381SN/A 1072381SN/Ainline MachInst 1082381SN/AmakeRegisterCopy(int dest, int src) 1092642Sstever@eecs.umich.edu{ 1102381SN/A panic("makeRegisterCopy not implemented"); 1112642Sstever@eecs.umich.edu return 0; 1122408SN/A} 1132408SN/A 1142409SN/A/** 1152408SN/A * Function to insure ISA semantics about 0 registers. 1162381SN/A * @param tc The thread context. 1172381SN/A */ 1182406SN/Atemplate <class TC> 1192406SN/Avoid zeroRegisters(TC *tc); 1202406SN/A 1212381SN/A// Alpha IPR register accessors 1222630SN/Ainline bool PcPAL(Addr addr) { return addr & 0x3; } 1232381SN/Ainline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 1242381SN/A 1252630SN/A//////////////////////////////////////////////////////////////////////// 1262381SN/A// 1272381SN/A// Translation stuff 1282630SN/A// 1292381SN/A 1302381SN/Ainline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1312381SN/A 1322381SN/A// User Virtual 1332381SN/Ainline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1342381SN/A 1352381SN/A// Kernel Direct Mapped 1362381SN/Ainline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1372657Ssaidi@eecs.umich.eduinline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1382381SN/A 1392381SN/A// Kernel Virtual 1402381SN/Ainline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1412381SN/A 1422381SN/Ainline Addr 1432381SN/ATruncPage(Addr addr) 1442406SN/A{ return addr & ~(PageBytes - 1); } 1452381SN/A 1462381SN/Ainline Addr 1472381SN/ARoundPage(Addr addr) 1482521SN/A{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1492521SN/A 1502381SN/Avoid initIPRs(ThreadContext *tc, int cpuId); 1512521SN/A#if FULL_SYSTEM 1522521SN/Avoid initCPU(ThreadContext *tc, int cpuId); 1532407SN/A 1542381SN/A/** 1552381SN/A * Function to check for and process any interrupts. 1562381SN/A * @param tc The thread context. 1572381SN/A */ 1582381SN/Atemplate <class TC> 1592381SN/Avoid processInterrupts(TC *tc); 1602381SN/A#endif 1612381SN/A 1622657Ssaidi@eecs.umich.eduvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1632381SN/A 1642381SN/Avoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1652381SN/A 1662630SN/A} // namespace AlphaISA 1672381SN/A 1682381SN/A#endif // __ARCH_ALPHA_UTILITY_HH__ 1692381SN/A