utility.hh revision 6329
12391SN/A/* 213998Stiago.muck@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38931Sandreas.hansson@arm.com * All rights reserved. 48931Sandreas.hansson@arm.com * 58931Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68931Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78931Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88931Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98931Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108931Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118931Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128931Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138931Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142391SN/A * this software without specific prior written permission. 152391SN/A * 162391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272391SN/A * 282391SN/A * Authors: Nathan Binkert 292391SN/A * Steve Reinhardt 302391SN/A */ 312391SN/A 322391SN/A#ifndef __ARCH_ALPHA_UTILITY_HH__ 332391SN/A#define __ARCH_ALPHA_UTILITY_HH__ 342391SN/A 352391SN/A#include "arch/alpha/types.hh" 362391SN/A#include "arch/alpha/isa_traits.hh" 372391SN/A#include "arch/alpha/miscregfile.hh" 382391SN/A#include "base/misc.hh" 392665SN/A#include "config/full_system.hh" 402665SN/A#include "cpu/thread_context.hh" 418931Sandreas.hansson@arm.com 422391SN/Anamespace AlphaISA { 432391SN/A 448931Sandreas.hansson@arm.comuint64_t getArgument(ThreadContext *tc, int number, bool fp); 458931Sandreas.hansson@arm.com 468931Sandreas.hansson@arm.cominline bool 472391SN/AinUserMode(ThreadContext *tc) 482391SN/A{ 4912492Sodanrc@yahoo.com.br return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 5012492Sodanrc@yahoo.com.br} 512391SN/A 5213853Sgabeblack@google.cominline bool 5313892Sgabeblack@google.comisCallerSaveIntegerRegister(unsigned int reg) 548931Sandreas.hansson@arm.com{ 5513892Sgabeblack@google.com panic("register classification not implemented"); 568719SN/A return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27; 572462SN/A} 589053Sdam.sunwoo@arm.com 599053Sdam.sunwoo@arm.cominline bool 609053Sdam.sunwoo@arm.comisCalleeSaveIntegerRegister(unsigned int reg) 618931Sandreas.hansson@arm.com{ 629293Sandreas.hansson@arm.com panic("register classification not implemented"); 639293Sandreas.hansson@arm.com return reg >= 9 && reg <= 15; 649293Sandreas.hansson@arm.com} 659293Sandreas.hansson@arm.com 669293Sandreas.hansson@arm.cominline bool 679293Sandreas.hansson@arm.comisCallerSaveFloatRegister(unsigned int reg) 689293Sandreas.hansson@arm.com{ 699293Sandreas.hansson@arm.com panic("register classification not implemented"); 709293Sandreas.hansson@arm.com return false; 719293Sandreas.hansson@arm.com} 729293Sandreas.hansson@arm.com 739293Sandreas.hansson@arm.cominline bool 749293Sandreas.hansson@arm.comisCalleeSaveFloatRegister(unsigned int reg) 759293Sandreas.hansson@arm.com{ 769293Sandreas.hansson@arm.com panic("register classification not implemented"); 779293Sandreas.hansson@arm.com return false; 789293Sandreas.hansson@arm.com} 7911005Sandreas.sandberg@arm.com 809293Sandreas.hansson@arm.cominline Addr 819293Sandreas.hansson@arm.comalignAddress(const Addr &addr, unsigned int nbytes) 829293Sandreas.hansson@arm.com{ 839293Sandreas.hansson@arm.com return (addr & ~(nbytes - 1)); 8412749Sgiacomo.travaglini@arm.com} 859293Sandreas.hansson@arm.com 8613998Stiago.muck@arm.com// Instruction address compression hooks 8713998Stiago.muck@arm.cominline Addr 889293Sandreas.hansson@arm.comrealPCToFetchPC(const Addr &addr) 899293Sandreas.hansson@arm.com{ 909293Sandreas.hansson@arm.com return addr; 9112749Sgiacomo.travaglini@arm.com} 9212749Sgiacomo.travaglini@arm.com 939293Sandreas.hansson@arm.cominline Addr 949293Sandreas.hansson@arm.comfetchPCToRealPC(const Addr &addr) 959293Sandreas.hansson@arm.com{ 969293Sandreas.hansson@arm.com return addr; 979293Sandreas.hansson@arm.com} 989293Sandreas.hansson@arm.com 999293Sandreas.hansson@arm.com// the size of "fetched" instructions (not necessarily the size 1009293Sandreas.hansson@arm.com// of real instructions for PISA) 1018931Sandreas.hansson@arm.cominline size_t 1028931Sandreas.hansson@arm.comfetchInstSize() 1038931Sandreas.hansson@arm.com{ 10413892Sgabeblack@google.com return sizeof(MachInst); 10513892Sgabeblack@google.com} 1068931Sandreas.hansson@arm.com 10713892Sgabeblack@google.cominline MachInst 1082391SN/AmakeRegisterCopy(int dest, int src) 1096107SN/A{ 1106107SN/A panic("makeRegisterCopy not implemented"); 1118931Sandreas.hansson@arm.com return 0; 1129235Sandreas.hansson@arm.com} 1132413SN/A 1148931Sandreas.hansson@arm.com/** 1158931Sandreas.hansson@arm.com * Function to insure ISA semantics about 0 registers. 1162413SN/A * @param tc The thread context. 11713853Sgabeblack@google.com */ 11813853Sgabeblack@google.comtemplate <class TC> 11913853Sgabeblack@google.comvoid zeroRegisters(TC *tc); 1208931Sandreas.hansson@arm.com 12111614Sdavid.j.hashe@gmail.com// Alpha IPR register accessors 1222413SN/Ainline bool PcPAL(Addr addr) { return addr & 0x3; } 1238931Sandreas.hansson@arm.cominline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 12411614Sdavid.j.hashe@gmail.com 12511614Sdavid.j.hashe@gmail.com//////////////////////////////////////////////////////////////////////// 12611614Sdavid.j.hashe@gmail.com// 12711614Sdavid.j.hashe@gmail.com// Translation stuff 1283170SN/A// 1293170SN/A 1303170SN/Ainline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1313170SN/A 1323170SN/A// User Virtual 1333170SN/Ainline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1343170SN/A 1354626SN/A// Kernel Direct Mapped 1363170SN/Ainline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1373170SN/Ainline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1383170SN/A 1393170SN/A// Kernel Virtual 1404626SN/Ainline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1413170SN/A 1423170SN/Ainline Addr 1433170SN/ATruncPage(Addr addr) 1443170SN/A{ return addr & ~(PageBytes - 1); } 1453170SN/A 1463170SN/Ainline Addr 1473170SN/ARoundPage(Addr addr) 1483170SN/A{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1494626SN/A 15012749Sgiacomo.travaglini@arm.comvoid initIPRs(ThreadContext *tc, int cpuId); 1513170SN/A#if FULL_SYSTEM 1523170SN/Avoid initCPU(ThreadContext *tc, int cpuId); 1536102SN/A 1546102SN/A/** 1554040SN/A * Function to check for and process any interrupts. 1563170SN/A * @param tc The thread context. 1576102SN/A */ 1583170SN/Atemplate <class TC> 1593170SN/Avoid processInterrupts(TC *tc); 1604626SN/A#endif 1613170SN/A 1623170SN/Avoid copyRegs(ThreadContext *src, ThreadContext *dest); 1633170SN/A 1648719SN/Avoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1659053Sdam.sunwoo@arm.com 1668719SN/A} // namespace AlphaISA 1679053Sdam.sunwoo@arm.com 1688719SN/A#endif // __ARCH_ALPHA_UTILITY_HH__ 1699053Sdam.sunwoo@arm.com